17

ATSAM2133B

2694A–DRMSD–05/03

Reset and Power-

down

During power-up, the RESET input should be held low until the crystal oscillator and

PLL are stabilized. This can take about 20 ms.

After the low-to-high transition of RESET, the following occurs:

•

Synthesis/DSP enters an idle state

•

P16 program execution starts from address 0100H in ROM space (WCS low)

If PDWN is asserted low, then the crystal oscillator and PLL are stopped. If the power

switch is used, then the chip enters a deep power-down sleep mode, as power is

removed from the core. To exit power down, PDWN must be asserted high, then

RESET applied.

Power-down mode is managed by an internal power switch. The equivalent schematic

and standard connection is shown on the diagram below.

All the VC2 pins must be connected to PWROUT.

Figure 10. Schematic

Note:

High level for PDWN is VC2 = 2.5V ±10%.

Figure 11. PDWN Connection

VC2 Source from

Power Supply

ATSAM2133B

VC2

VC2

VC2

VC2

VC2

VC2

PDWN = L: Power-down Mode (Internal Power Switch Open)

PDWN = H: Operating Mode (Internal Power Switch Closed)

ATSAM2133B

VC2

HOST

PDWN

Control

(High level = 3.3V)

VC3

3.3V

10 kOhm

PDWN

VC3

3.3V

PWRIN

2.5V

PWROUT