AT77C104B datasheet(21/36 Pages) ATMEL

21 / 36 page

AT77C104B

5347B–BIOM–08/04

Polarity configures the clock’s idle level, which is high ('1') during polarity one of the

operation and low ('0') during polarity zero of the operation.

AT77C104B and the SPI

The AT77C104B is always the slave and the host always the master. The host drives

the SCK clock. Both the AT77C104B and the host transmit data with the MISO signal.

The word length of the transferred data is fixed to 8 bits. The Most Significant Bit (MSB)

is sent first.

The AT77C104B supports only one phase and polarity configuration:

•

The clock’s idle level set to high (polarity 1)

•

The output data changed on the clock’s falling edge, and input data shifted in on the

clock’s rising edge (phase 0).

Figure 9. SPI Waveform (Phase = 0, Polarity = 1)

Note:

During initialization of the SCK wire (power-on or reset), SS/ has to be inactive (‘1’).

Recommendations

The SSS or FSS falling edge should be half a clock cycle before the first SCK falling

edge and the SSS or FSS rising edge should be half a clock cycle after the last SCK

rising edge.

SPI Behavior with

Hazardous Access

The control register block uses an internal finite state machine that can only be initial-

ized by the RST pin (asynchronous reset). When SPI access does not use 8 clock

pulses, the internal finite state machine is desynchronized. The only way to resynchro-

nize it is by resetting the sensor with the RST pin. No requester modification is recorded

when a write access is made on a read-only register. Reliable initialization of read-only

registers is not guaranteed when the slow SPI’s maximum clock frequency is not

respected.

SCK

MOSI/MISO

SS/

Emission

Reception

MSB

LSB

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