PCA9541 datasheet(13/30 Pages) PHILIPS

13 / 30 page

Philips Semiconductors

Product data sheet

PCA9541

2-to-1 I2C master selector with interrupt logic and reset

2004 Oct 01

POWER-ON RESET

When power is applied to VDD, an internal Power-On Reset holds

the PCA9541 in a reset condition until VDD has reached VPOR. At

this point, the reset condition is released and the internal registers

are initialized to their default states, with:

Default

Stop Detect

PCA9541/01

Channel 0

PCA9541/02

Channel 0

PCA9541/03

No Channel

1. PCA9541/01: after power-up and/or insertion of the device in the

main I2C-bus, the upstream Channel 0 and the downstream

slave channel are connected together.

2. PCA9541/02: after power-up and/or insertion of the device in the

main I2C-bus, the upstream Channel 0 and the downstream

slave channel are connected together after a STOP condition

has been detected by the PCA9541/02 on Channel 0.

– If the bus was not idle, Channel 0 and the downstream slave

device will be connected together as soon as a STOP

condition occurs at the conclusion of the transmission

sequence on Channel 0.

– If the bus was idle, then Channel 0 is connected to the

downstream slave channel after a STOP condition is detected

on Channel 0. This I2C-bus command may or may not be

addressed to the PCA9541/02.

– If a switch to channel 1 (initiated by the master on channel 1)

is requested (before or after the default switch to Channel 0

has been performed), the upstream channel 1 is connected to

the downstream slave channel when the master located in

Channel 1 sends the STOP command.

3. PCA9541/03: after power-up and/or insertion of the device in the

main I2C-bus, no channel will be connected to the downstream

channel. The device is ready to receive a START condition and

its address by a master.

If either register writes to its Control Register, then the

connection between the upstream and the downstream channels

is determined by the values on the Control Registers.

Thereafter, VDD must be lowered below 0.2 V to reset the device.

EXTERNAL RESET

A reset can be accomplished by holding the RESET pin LOW for a

minimum of tW. The PCA9541 registers and I2C state machine will

be held in their default states until the RESET input is once again

HIGH. This input typically requires a pull-up resistor to VDD.

Default states are:

–I2C upstream Channel 0 connected to the I2C downstream

channel for the PCA9541/01

– no I2C upstream channel connected to the I2C downstream

channel for the PCA9541/02 with Channel 0 connected to the

downstream I2C channel after detection of a STOP on the

upstream channel.

– no I2C upstream channel connected to the I2C downstream

channel for the PCA9541/03.

VOLTAGE TRANSLATION

The pass gate transistors of the PCA9541 are constructed such that

the VDD voltage can be used to limit the maximum voltage that will

be passed from one I2C-bus to another.

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

Vpass vs. VDD

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Vpass

VDD

MINIMUM

TYPICAL

MAXIMUM

SW00820

2.0

Figure 7. Vpass voltage

Figure 7 shows the voltage characteristics of the pass gate

transistors (note that the graph was generated using the data

specified in the DC Characteristics section of this datasheet). In

order for the PCA9541 to act as a voltage translator, the Vpass

voltage should be equal to, or lower than the lowest bus voltage. For

example, if the main buses were running at 5 V, and the

downstream bus was 3.3 V, then Vpass should be equal to or below

3.3 V to effectively clamp the downstream bus voltages. Looking at

Figure 7, we see that Vpass (max.) will be at 3.3 V when the

PCA9541 supply voltage is 3.5 V or lower so the PCA9541 supply

voltage could be set to 3.3 V. Pull-up resistors can then be used to

bring the bus voltages to their appropriate levels (see Figure 16).

More Information on voltage translation can be found in Application

Note AN262

PCA954X family of I2C/SMBus multiplexers and

switches.

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