MS82C55A datasheet(4/26 Pages) RENESAS

4 / 26 page

MS82C55A, MQ82C55A, MP82C55A

FN6140 Rev 2.00

Page 4 of 26

June 15, 2006

Functional Description

Data Bus Buffer

This three-state bidirectional 8-bit buffer is used to interface the

82C55A to the system data bus. Data is transmitted or

received by the buffer upon execution of input or output

instructions by the CPU. Control words and status information

are also transferred through the data bus buffer.

Read/Write and Control Logic

The function of this block is to manage all of the internal and

external transfers of both Data and Control or Status words. It

accepts inputs from the CPU Address and Control busses and

in turn, issues commands to both of the Control Groups.

(CS) Chip Select. A “low” on this input pin enables the

communication between the 82C55A and the CPU.

(RD) Read. A “low” on this input pin enables 82C55A to send

the data or status information to the CPU on the data bus. In

essence, it allows the CPU to “read from” the 82C55A.

(WR) Write. A “low” on this input pin enables the CPU to write

data or control words into the 82C55A.

(A0 and A1) Port Select 0 and Port Select 1. These input

signals, in conjunction with the RD and WR inputs, control the

selection of one of the three ports or the control word register.

They are normally connected to the least significant bits of the

address bus (A0 and A1).

(RESET) Reset. A “high” on this input initializes the control

Group A and Group B Controls

The functional configuration of each port is programmed by the

systems software. In essence, the CPU “outputs” a control

word to the 82C55A. The control word contains information

such as “mode”, “bit set”, “bit reset”, etc., that initializes the

functional configuration of the 82C55A.

Each of the Control blocks (Group A and Group B) accepts

“commands” from the Read/Write Control logic, receives

“control words” from the internal data bus and issues the

proper commands to its associated ports.

Control Group A - Port A and Port C upper (C7 - C4)

Control Group B - Port B and Port C lower (C3 - C0)

The control word register can be both written and read as

shown in the “Basic Operation” table. Figure 4 shows the

control word format for both Read and Write operations. When

the control word is read, bit D7 will always be a logic “1”, as this

implies control word mode information.

Ports A, B, and C

The 82C55A contains three 8-bit ports (A, B, and C). All can be

configured to a wide variety of functional characteristics by the

system software but each has its own special features or

“personality” to further enhance the power and flexibility of the

82C55A.

Port A One 8-bit data output latch/buffer and one 8-bit data

input latch.

Port B One 8-bit data input/output latch/buffer and one 8-bit

data input buffer.

Port C One 8-bit data output latch/buffer and one 8-bit data input

buffer (no latch for input). This port can be divided into two 4-bit

ports under the mode control. Each 4-bit port contains a 4-bit

latch and it can be used for the control signal output and status

signal inputs in conjunction with ports A and B.

82C55A BASIC OPERATION

INPUT OPERATION

(READ)

00010

Port A

Data Bus

01010

Port B

Data Bus

10010

Port C

Data Bus

11010

Control Word

Data Bus

OUTPUT OPERATION

(WRITE)

00100

Data Bus

Port A

01100

Data Bus

Port B

10100

Data Bus

Port C

11100

Data Bus

Control

DISABLE FUNCTION

XXXX

Data Bus

Three-State

110

Data Bus

Three-State

FIGURE 2. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,

READ/WRITE, GROUP A & B CONTROL LOGIC

FUNCTIONS

GROUP A

PORT A

(8)

GROUP A

PORT C

UPPER

(4)

GROUP B

PORT C

LOWER

(4)

GROUP B

PORT B

(8)

GROUP B

CONTROL

GROUP A

CONTROL

DATA

READ

WRITE

CONTROL

LOGIC

RESET

D7-D0

POWER

SUPPLIES

+5V

GND

BIDIRECTIONAL

DATA BUS

I/O

PA7-

I/O

PC7-

I/O

PC3-

I/O

PB7-

BUFFER

BUS

PB0

PC0

PC4

PA0

8-BIT

INTERNAL

DATA BUS

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