KMB-001LEVALZ datasheet(22/34 Pages) RENESAS

22 / 34 page

ISLA214P12

FN7982 Rev 2.00

Page 22 of 34

June 27, 2012

The power-down mode can also be controlled through the SPI

port, which overrides the NAPSLP pin setting. Details on this are

contained in “Serial Peripheral Interface” on page 25.

Data Format

Output data can be presented in three formats: two’s

complement (default), Gray code and offset binary. The data

format can be controlled through the SPI port, by writing to

address 0x73. Details on this are contained in “Serial Peripheral

Interface” on page 25.

Offset binary coding maps the most negative input voltage to

code 0x000 (all zeros) and the most positive input to 0xFFF (all

ones). Two’s complement coding simply complements the MSB

of the offset binary representation.

When calculating Gray code the MSB is unchanged. The

remaining bits are computed as the XOR of the current bit

position and the next most significant bit. Figure 33 shows this

operation.

Converting back to offset binary from Gray code must be done

recursively, using the result of each bit for the next lower bit as

shown in Figure 34.

Mapping of the input voltage to the various data formats is

shown in Table 3.

Clock Divider Synchronous Reset

An output clock (CLKOUTP, CLKOUTN) is provided to facilitate

latching of the sampled data. The output clock frequency is

equal to the input clock frequency divided by the internal clock

divider setting. (See clock input description).

For clock divide settings > ‘1’, the absolute phase of the output

clocks for multiple A/Ds is indeterminate - there will be a phase

ambiguity between the output clocks of ADCs in a multiple ADC

system. The CLKDIVRST feature allows the phase of multiple

A/Ds to be synchronized (see Figure35) when the internal clock

divider is used, greatly simplifying data capture in systems

employing multiple A/Ds. For clock divide setting=’1’, there is no

phase ambiguity between clock outputs in a multiple ADC

system and CLKDIVRST can be left as a DNC (do not connect)

The CLKDIVRST signal must be well-timed with respect to the

sample clock (See “Switching Specifications” on page 13). Figure

35 shows assertion of CLKDIVRSTP by a positive edge

(CLKDIVRSTN must be driven but is not shown); CLKDIVRSTP can

remain high indefinitely after a synchronization event.

CLKDIVRSTP can also be a pulse if needed, with CLKDIVRSTP

returning to a logic ‘0’ after assertion; in this case the CLKDIVRST

pulse width should be a minimum of 3 input sample clock

periods. In applications where multiple CLKDIVRST pulse events

are required a user should wait a minimum of 30 clock cycles

before starting a second CLKDIVRST pulse event.

It will take a maximum of 30 input clock cycles to attain

synchronization (tRSTRT) in applications where the input clock is

not interrupted; if the input clock is interrupted CLKOUT will be

static or indeterminate until synchronization is attained.

In some applications, interrupting the input sample clock briefly

(~ 150 cycles max) can simplify the timing requirements for

synchronization using CLKDIVRST), in this case the total

CLKDIVRST recovery time will increase by the number of input

clock cycles the sample clock is held static. Valid data is

available (after recovery) in all cases after the normal pipeline

latency. Assertion of CLKDIVRST resets

Intersil Application Note 1604 describes the synchronization of

multiple ISLA1xxP50s. This document discusses the topic of

synchronization in more detail and can be used to better

understand the ISLA2XXPxx ADCs’ operation.

FIGURE 33. BINARY TO GRAY CODE CONVERSION

BINARY

GRAY CODE

• • • •

FIGURE 34. GRAY CODE TO BINARY CONVERSION

BINARY

GRAY CODE

• • • •

TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING

INPUT

VOLTAGE

OFFSET BINARY

TWO’S

COMPLEMENT

GRAY CODE

–Full Scale 00 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000

–Full Scale

+ 1LSB

00 0000 0000 0001 10 0000 0000 0001 00 0000 0000 0001

Mid–Scale 10 0000 0000 0000 00 0000 0000 0000 11 0000 0000 0000

+Full Scale

– 1LSB

11 1111 1111 1110 01 1111 1111 1110 10 0000 0000 0001

+Full Scale 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000

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