ISL28107 datasheet(19/31 Pages) RENESAS

19 / 31 page

ISL28107, ISL28207, ISL28407

FN6631 Rev 8.00

Page 19 of 31

September 29, 2015

Applications Information

Functional Description

The ISL28107, ISL28207 and ISL28407 are single, dual and

quad, very low 1/f noise (14nV/

Hz @ 10Hz) precision op-amps.

These amplifiers feature very high open loop gain (50kV/mV) for

excellent CMRR (145dB) and gain accuracy. Both devices are

fabricated in a new precision 40V complementary bipolar DI

process.

The super-beta NPN input stage with bias current cancellation

provides bipolar-like levels of AC performance, with the low input

bias currents approaching JFET levels. The temperature

stabilization provided by bias current cancellation removes the

high input bias current temperature coefficient commonly found

in JFET amplifiers. Figures 9 and 10 show the input bias current

variation over temperature.

The input offset voltage (VOS) has a very low, worst case value of

75µV max at +25°C and a maximum TC of 0.65µV/°C. Figure 38

shows VOS as a function of supply voltage and temperature with

the common mode voltage at 0V for split supply operation.

The complementary bipolar output stage maintains stability

driving large capacitive loads (to 10nF) without external

compensation. The small signal overshoot vs. load capacitance is

shown in Figure 54.

Operating Voltage Range

The devices are designed to operate over the 4.5V (±2.25V) to

40V (±20V) range and are fully characterized at 10V (±5V) and

30V (±15V). Both DC and AC performance remain virtually

unchanged over the complete 4.5V to 40V operating voltage

range. Parameter variation with operating voltage is shown in the

“Typical Performance Curves” beginning on page 11. The input

common mode voltage range sensitivity to temperature is shown

in Figure 38 (±15V).

Input ESD Diode Protection

The input terminals (IN+ and IN-) each have internal ESD

protection diodes to the positive and negative supply rails, a series

connected 500

 current limiting resistor followed by an

anti-parallel diode pair across the input NPN transistors (Circuit 1

in “Pin Descriptions” on page 4).

FIGURE 51. SMALL SIGNAL TRANSIENT RESPONSE VS = ±5V,

±15V, ±20V

FIGURE 52. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,

VS =±15V

FIGURE 53. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, VS =

±15V

FIGURE 54. % OVERSHOOT vs LOAD CAPACITANCE, VS = ±15V

Typical Performance Curves V

S = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise specified. (Continued)

TIME (µs)

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

RL = 2k, 10k

AV = 1

CL = 4pF

VOUT = 100mVP-P

VS = ±5V, ±15V, ±20V

TIME (µs)

-0.06

-0.02

0.02

0.06

0.10

0.14

0.18

0.22

0.26

100 120 140 160 180 200

-1

INPUT

OUTPUT

VS = ±15V

RL = 10k

AV = 100

CL = 4pF

Rf = 10k, Rg = 100

VIN = 200mVP-P

TIME (µs)

-0.26

-0.22

-0.18

-0.14

-0.10

-0.06

-0.02

0.02

0.06

100 120 140 160 180 200

-15

-13

-11

-9

-7

-5

-3

-1

INPUT

OUTPUT

VS = ±15V

RL = 10k

AV = 100

CL = 4pF

Rf = 10k, Rg = 100

VIN = 200mVP-P

CAPACITANCE (pF)

100

1,000

10,000

T -

VS = ±15V

RL = 10k

AV = 1

VOUT = 100mVP-P

T +

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