DSPIC30F6014 datasheet(49/222 Pages) MICROCHIP

49 / 222 page

 2004 Microchip Technology Inc.

Preliminary

DS70117C-page 47

dsPIC30F6011/6012/6013/6014

FIGURE 5-2:

INTERRUPT STACK

FRAME

The RETFIE (return from interrupt) instruction will

unstack the program counter and STATUS registers to

return the processor to its state prior to the interrupt

sequence.

5.5

Alternate Vector Table

In program memory, the Interrupt Vector Table (IVT) is

followed by the Alternate Interrupt Vector Table (AIVT),

as shown in Table 5-1. Access to the alternate vector

table is provided by the ALTIVT bit in the INTCON2 reg-

ister. If the ALTIVT bit is set, all interrupt and exception

processes will use the alternate vectors instead of the

default vectors. The alternate vectors are organized in

the same manner as the default vectors. The AIVT sup-

ports emulation and debugging efforts by providing a

means to switch between an application and a support

environment without requiring the interrupt vectors to

be reprogrammed. This feature also enables switching

between

applications

for

evaluation

different

software algorithms at run time.

If the AIVT is not required, the program memory allo-

cated to the AIVT may be used for other purposes.

AIVT is not a protected section and may be freely

programmed by the user.

5.6

Fast Context Saving

A context saving option is available using shadow reg-

isters. Shadow registers are provided for the DC, N,

OV, Z and C bits in SR, and the registers W0 through

W3. The shadows are only one level deep. The shadow

registers are accessible using the PUSH.S and POP.S

instructions only.

When the processor vectors to an interrupt, the

PUSH.S

instruction can be used to store the current

value of the aforementioned registers into their

respective shadow registers.

If an ISR of a certain priority uses the PUSH.S and

POP.S

instructions for fast context saving, then a

higher priority ISR should not include the same instruc-

tions. Users must save the key registers in software

during a lower priority interrupt if the higher priority ISR

uses fast context saving.

5.7

External Interrupt Requests

The interrupt controller supports up to five external

interrupt request signals, INT0-INT4. These inputs are

edge sensitive; they require a low-to-high or a high-to-

low transition to generate an interrupt request. The

INTCON2 register has five bits, INT0EP-INT4EP, that

select the polarity of the edge detection circuitry.

5.8

Wake-up from Sleep and Idle

The interrupt controller may be used to wake-up the

processor from either Sleep or Idle modes, if Sleep or

Idle mode is active when the interrupt is generated.

If an enabled interrupt request of sufficient priority is

received by the interrupt controller, then the standard

interrupt request is presented to the processor. At the

same time, the processor will wake-up from Sleep or

Idle and begin execution of the Interrupt Service

Routine (ISR) needed to process the interrupt request.

Note 1: The user can always lower the priority

level by writing a new value into SR. The

Interrupt Service Routine must clear the

interrupt flag bits in the IFSx register

before lowering the processor interrupt

priority, in order to avoid recursive

interrupts.

2: The IPL3 bit (CORCON<3>) is always

clear when interrupts are being pro-

cessed. It is set only during execution of

traps.

W15 (before CALL)

W15 (after CALL)

0x0000

PC<15:0>

SRL IPL3 PC<22:16>

POP : [--W15]

PUSH : [W15++]

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