HIP9011

FN4367 Rev 2.00

Page 2 of 11

January 6, 2006

Pinout

HIP9011

(SOIC)

TOP VIEW

11

12

13

14

15

16

17

18

20

19

10

9

8

7

6

5

4

3

2

1

VMID

INTOUT

INT/HOLD

CS

SO

SI

SCK

TEST

CH1IN

CH1FB

CH0FB

CH0IN

GND

NC

NC

OSCIN

OSCOUT

CH0NI

CH1NI

Pin Descriptions

PIN

NUMBER

DESIGNATION

DESCRIPTION

Five volt power input.

2

GND

This pin is tied to ground.

This pin is connected to the internal mid-supply generator and is brought out for bypassing by a 0.022

F capacitor.

4

INTOUT

Buffered output of the integrator. Output signal is held by an internal Sample and Hold circuit when INT/HOLD is

low.

5, 6

NC

These pins are not internally connected. Do Not Use.

7INT/HOLD

Selects whether the chip is in the Integrate Mode (Input High) or in the Hold Mode (Input Low). This pin has an

internal pull down.

8CS

A low input on this pin enables the chip to communicate over the SPI bus. This pin has an internal pull-up.

9

OSCIN

Input to inverter used for the oscillator circuit. A 4MHz crystal or ceramic resonator is connected between this pin and

pin 10. To bias the inverter, a 1.0M

 to 10M resistor is usually connected between this pin and pin 10.

10

OSCOUT

Output of the inverter used for the oscillator. See pin 9 above.

11

SO

Output of the chip SPI data bus. This is a three-state output that is controlled via the SPI bus. The output is

placed in the high impedance state by setting CS high when the chip is not selected. This high impedance state

can also be programmed by setting the LSB of the prescaler word to 1. This will take precedence over CS. A 0

enables the active state. The Diagnostic Mode overrides these conditions.

12

SI

Input of the chip SPI data bus. Data length is eight bits. This pin has an internal pull-up.

13

SCK

Input from the SPI clock. Normally low, the data is transferred to the chip internal circuitry on the falling clock

edge. This pin has an internal pull up.

14

TEST

A low on this pin places the chip in the diagnostic mode. For normal operation this pin is tied high or left open.

This pin has an internal pull up.

15

CH1NI

Non-inverting input of Channel one.

16

CH1IN

Inverting input to channel one amplifier. A resistor is tied from this summing input to the transducer. A second

resistor is tied between this pin and pin 17, CH1FB to establish the gain of the amplifier.

17

CH1FB

Output of the channel one amplifier. This pin is used to apply feedback.

18

CH0FB

Output of the channel zero amplifier. This pin is used to apply feedback.

19

CH0IN

Inverting input to channel zero amplifier. Remainder same as channel one amplifier except feedback is applied

from pin 18.

20

CH0NI

Non-inverting input of Channel 0. Remainder the same as pin 16, except feedback is applied from terminal 18.