ISL97701 datasheet(8/11 Pages) RENESAS

8 / 11 page

ISL97701

FN6474 Rev 1.00

Page 8 of 11

February 22, 2008

some cases disable the ISL97701 boost function as long as

the fault is present.

Maximum Duty Cycle – LX

The maximum duty cycle Dmax, at which the power FET can

operate defines the upper limit of the regulator output to input

voltage ratio according to Equation 2:

In the ISL97701, DMAX is defined from the minimum off-time

tOFF(LX)min and the switching frequency.

If NSYNC is tied to VDD the internal oscillator defines DMAX

according to Equation 3:

With external synchronization at pin NSYNC:

The duty cycle at LX can be 0% (pulse skipping), if the output

voltage exceeds the target voltage set with the feedback

resistors.

Internal Schottky Diode – LX, VOUT

The inductor node LX internally connects to the power FET

and to the anode of the integrated power Schottky diode. The

cathode of the diode is pin VOUT. An overvoltage detector at

VOUT continuously monitors the cathode voltage and

immediately disables the boost regulator if the voltage exceeds

the maximum allowable voltage.

External Synchronization Pin - NSYNC

Pin NSYNC can be used to synchronize the LX output pin with an

external clock signal in the range from 600kHz to 1.4MHz.

A frequency detector monitoring NSYNC enables external

synchronization if f(NSYNC) is higher than ~300kHz. If the pin

is, for example, static high, the internal oscillator defines the LX

output frequency and phase. When externally synchronized, all

falling edges at LX are timed from the falling edge of the clock

signal applied at NSYNC. The timing of the rising edge at LX is

defined by the boost controller.

TABLE 1. FAULT PROTECTION

FAULT

DESCRIPTION

FAULT

CONDITION

ISL97701 FAULT REACTION

Undervoltage at

VDD

V(VDD) <

V(VDD)off

Disables I/Os and waits until

V(VDD) reaches V(VDD)on to

begin with the start-up sequence

Overcurrent

drawn from

VDDOUT

I(VDDOUT) >

It(VDDOUT)err

Disables VDDOUT switch and

LX driver and immediately

restarts the start-up sequence

Overvoltage at

VOUT

V(VOUT) >

Vt(VOUT)err

Disables VDDOUT switch and

LX driver and waits until output

voltage V(VOUT) drops to

Vt(VOUT) to restart the start-up

sequence

Over-Temperature

on chip

Tj > Toff

Disables VDDOUT switch and

LX driver and waits until junction

temp drops to “Ton” to restart the

start-up sequence

VOUT

VIN

----------------

1DMAX

–

--------------------------

(EQ. 2)

DMAX fOSC

 1t

OFF LX

min f

OSC



–

(EQ. 3)

DMAX NSYNC

 1t

OFF LX

min f NSYNC





–

(EQ. 4)

V(NSYNC)

V(LX)

FIGURE 15. NSYNC TO LX SYNCHRONIZATION DELAY

V(NSYNC)

V(LX)

FIGURE 16. LX SYNCHRONIZATION WITH f(SYNC) = 600kHz

FIGURE 17. LX SYNCHRONIZATION WITH f(SYNC) = 1.4MHz

V(NSYNC)

V(LX)

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