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EL5423 датащи(PDF) 13 Page - Renesas Technology Corp

номер детали EL5423
подробное описание детали  12MHz 4-, 8-, 10- and 12-Channel Rail-to-Rail Input-Output Buffers
PDF  17 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

EL5423 датащи(HTML) 13 Page - Renesas Technology Corp

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EL5123, EL5223, EL5323, EL5423
FN7176 Rev 3.00
Page 13 of 17
August 31, 2010
when sourcing, and
when sinking.
where:
i = 1 to Total number of buffers
VS = Total supply voltage
ISMAX = Maximum quiescent current per channel
VOUTi = Maximum output voltage of the application
ILOADi = Load current
If we set the Equations 2 and 3 equal to each other, we can
solve for RLOADi to avoid device overheat. The package power
dissipation curves provide a convenient way to see if the
device will overheat. The maximum safe power dissipation can
be found graphically, based on the package type and the
ambient temperature. By using the previous equation, it is a
simple matter to see if PDMAX exceeds the device's power
derating curves.
Unused Buffers
It is recommended that any unused buffer have the input tied to
the ground plane.
Driving Capacitive Loads
The EL5123, EL5223, EL5323, and EL5423 can drive a wide
range of capacitive loads. As load capacitance increases,
however, the -3dB bandwidth of the device will decrease and
the peaking increase. The buffers drive 10pF loads in parallel
with 10k
 with just 1.5dB of peaking, and 100pF with 6.4dB of
peaking. If less peaking is desired in these applications, a
small series resistor (usually between 5
 and 50) can be
placed in series with the output. However, this will obviously
reduce the gain slightly. Another method of reducing peaking is
to add a “snubber” circuit at the output. A snubber is a shunt
load consisting of a resistor in series with a capacitor. Values of
150
 and 10nF are typical. The advantage of a snubber is that
it does not draw any DC load current or reduce the gain.
Power Supply Bypassing and Printed Circuit Board
Layout
As with any high frequency device, good printed circuit board
layout is necessary for optimum performance. Ground plane
construction is highly recommended, lead lengths should be as
short as possible, and the power supply pins must be well
bypassed to reduce the risk of oscillation. For normal single
supply operation, where the VS- pin is connected to ground, a
0.1µF ceramic capacitor should be placed from VS+ pin to
ground. A 4.7µF tantalum capacitor should then be connected
from VS+ pin to ground. One 4.7µF capacitor may be used for
multiple devices. This same capacitor combination should be
placed at each supply pin to ground if split supplies are to be
used.
PDMAX
iV
S
ISMAX V
OUTiVS- 
ILOADi
+

=
(EQ. 3)



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