ISL6336DIRZ datasheet(21/30 Pages) RENESAS

21 / 30 page

ISL6336D

FN8320 Rev 0.00

Page 21 of 30

Oct 6, 2014

The soft-start time is the sum of the 4 periods, as shown in

Equation 13.

tD1 is a fixed delay with the typical value as 1.36ms. tD3 is

determined by the fixed 85µs plus the time to obtain valid VID

voltage. If the VID is valid before the output reaches the 1.1V, the

minimum time to validate the VID input is 500ns. Therefore, the

minimum tD3 is about 86µs.

During tD2 and tD4, ISL6336D digitally controls the DAC voltage

change at 6.25mV per step. The time for each step is determined

by the frequency of the soft-start oscillator, which is defined by

the resistor RSS from SS pin to GND. The second soft-start ramp

time tD2 and tD4 can be calculated based on Equations 14

and 15:

For example, when VID is set to 1.5V and RSS is set at 100kΩ, the

first soft-start ramp time tD2 will be 704µs and the second soft-

start ramp time tD4 will be 256µs.

After the DAC voltage reaches the final VID setting, VR_RDY will

be set to high with the fixed delay tD5. The typical value for tD5 is

85µs. Before the VR_RDY is released, the controller disregards

the PSI# input and always operates in normal CCM PWM mode.

Current Sense Output

The current flowing out of the IMON pin is equal to the sensed

average current inside ISL6336D. In typical applications, a

resistor is placed from the IMON pin to GND to generate a

voltage, which is proportional to the load current and the resistor

value, as shown in Equation 16:

where VIMON is the voltage at the IMON pin, RIOUT is the resistor

between the IMON pin and GND, ILOAD is the total output current

of the converter, RISEN is the sense resistor connected to the

ISEN+ pin, N is the active channel number, and RX is the DC

resistance of the current sense element, either the DCR of the

inductor or RSENSE depending on the sensing method.

The resistor from the IMON pin to GND should be chosen to

ensure that the voltage at the IMON pin is less than 1.11V under

the maximum load current. If the IMON pin voltage is higher than

1.11V, overcurrent shutdown will be triggered, as described in

“Overcurrent Protection” on page 22.

A small capacitor can be placed between the IMON pin and GND

to reduce the noise impact. If this pin is not used, tie it to GND.

Fault Monitoring and Protection

The ISL6336D actively monitors output voltage and current to

detect fault conditions. Fault monitors trigger protective

measures to prevent damage to a microprocessor load. One

common power-good indicator is provided for linking to external

system monitors. The schematic in Figure 15 outlines the

interaction between the fault monitors and the VR_RDY signal.

VR_RDY Signal

The VR_RDY pin is an open-drain logic output which indicates

that the soft-start period is complete and the output voltage is

within the regulated range. VR_RDY is pulled low during

shutdown and releases high after a successful soft-start and a

fixed delay tD5. VR_RDY will be pulled low when an undervoltage

or overvoltage condition is detected, or the controller is disabled

by a reset from EN_PWR, EN_VTT, POR, or VID OFF-code.

Undervoltage Detection

The undervoltage threshold is set at 50% of the VID code. When

the output voltage at VSEN is below the undervoltage threshold,

VR_RDY is pulled low.

Overvoltage Protection

Regardless of the VR being enabled or not, the ISL6336D

overvoltage protection (OVP) circuit will be active after its POR.

The OVP thresholds are different under different operation

conditions. When VR is not enabled and during the soft-start

intervals tD1, tD2 and tD3, the OVP threshold is 1.273V. Once the

controller detects valid VID input, the OVP trip point will be

changed to DAC plus 175mV.

Two actions are taken by ISL6336D to protect the

microprocessor load when an overvoltage condition occurs.

At the inception of an overvoltage event, all PWM outputs are

commanded low instantly (less than 20ns). This causes the

Intersil drivers to turn on the lower MOSFETs and pull the output

voltage below a level to avoid damaging the load. When the

VDIFF voltage falls below the DAC plus 75mV, PWM signals enter

a high-impedance state. The Intersil drivers respond to the

high-impedance input by turning off both upper and lower

MOSFETs. If the overvoltage condition reoccurs, ISL6336D will

again command the lower MOSFETs to turn on. The ISL6336D

will continue to protect the load in this fashion as long as the

overvoltage condition occurs.

Once an overvoltage condition is detected, normal PWM

operation ceases until ISL6336D is reset. Cycling the voltage on

EN_PWR, EN_VTT or VCC below the POR-falling threshold will

tSS

tD1 tD2 tD3 tD4

(EQ. 13)

tD2

1.1xRSS

6.25x25

------------------------

s



(EQ. 14)

tD4

VVID 1.1

–

xR

6.25x25

------------------------------------------------

s



(EQ. 15)

FIGURE 14. SOFT-START WAVEFORMS

VOUT, 500mV/DIV

EN_VTT

500µs/DIV

tD3 tD4 tD5

VR_RDY

tD1

tD2

VIMON

RIOUT

-------------------

RISEN

------------------ILOAD

(EQ. 16)

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