ISL5861SLASH2IAZ datasheet(5/14 Pages) RENESAS

5 / 14 page

ISL5861

FN6008 Rev 3.00

Page 5 of 14

Oct 7, 2015

Spurious Free Dynamic Range,

SFDR to Nyquist (fCLK/2)

fCLK = 210MSPS, fOUT = 80.8MHz (Notes 4, 7)

dBc

fCLK = 210MSPS, fOUT = 40.4MHz (Notes 4, 7, 9)

dBc

fCLK = 200MSPS, fOUT = 20.2MHz, T = 25oC (Notes 4, 7)

dBc

fCLK = 200MSPS, fOUT = 20.2MHz, T = -40oC to 85oC (Notes 4, 7)

dBc

fCLK = 130MSPS, fOUT = 50.5MHz (Notes 4, 7)

dBc

fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 7)

dBc

fCLK = 130MSPS, fOUT = 20.2MHz (Notes 4, 7)

dBc

fCLK = 130MSPS, fOUT = 10.1MHz (Notes 4, 7)

dBc

fCLK = 130MSPS, fOUT = 5.05MHz, T = 25oC (Notes 4, 7)

dBc

fCLK = 130MSPS, fOUT = 5.05MHz, T = -40oC to 85oC (Notes 4, 7)

dBc

fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 7)

dBc

fCLK = 80MSPS, fOUT = 30.3MHz (Notes 4, 7)

dBc

fCLK = 80MSPS, fOUT = 20.2MHz (Notes 4, 7)

dBc

fCLK = 80MSPS, fOUT = 10.1MHz (Notes 4, 7, 9)

dBc

fCLK = 80MSPS, fOUT = 5.05MHz (Notes 4, 7)

dBc

fCLK = 50MSPS, fOUT = 20.2MHz (Notes 4, 7)

dBc

fCLK = 50MSPS, fOUT = 10.1MHz (Notes 4, 7)

dBc

fCLK = 50MSPS, fOUT = 5.05MHz (Notes 4, 7)

dBc

Spurious Free Dynamic Range,

SFDR in a Window with Eight Tones

fCLK = 210MSPS, fOUT = 28.3MHz to 45.2MHz, 2.1MHz Spacing,

50MHz Span (Notes 4, 7, 9)

-65

dBc

fCLK = 130MSPS, fOUT =17.5MHz to 27.9MHz, 1.3MHz Spacing,

35MHz Span (Notes 4, 7)

-68

dBc

fCLK = 80MSPS, fOUT = 10.8MHz to 17.2MHz, 811kHz Spacing,

15MHz Span (Notes 4, 7)

-75

dBc

fCLK = 50MSPS, fOUT = 6.7MHz to 10.8MHz, 490kHz Spacing,

10MHz Span (Notes 4, 7)

-77

dBc

Spurious Free Dynamic Range,

SFDR in a Window with EDGE or GSM

fCLK = 78MSPS, fOUT = 11MHz, in a 20MHz Window, RBW=30kHz

(Notes 4, 7, 9)

-90

dBc

Adjacent Channel Power Ratio,

ACPR with UMTS

fCLK = 76.8MSPS, fOUT = 19.2MHz, RBW=30kHz (Notes 4, 7, 9)

VOLTAGE REFERENCE

Internal Reference Voltage, VFSADJ

Pin 18 Voltage with Internal Reference

1.2

1.23

1.3

Internal Reference Voltage Drift

40

ppm/oC

Internal Reference Output Current

Sink/Source Capability

Reference is not intended to be externally loaded

A

Reference Input Impedance

-1



Reference Input Multiplying Bandwidth (Note 7)

1.0

MHz

DIGITAL INPUTS D11-D0, CLK

Input Logic High Voltage with

3.3V Supply, VIH

(Note 3)

2.3

3.3

Input Logic Low Voltage with

3.3V Supply, VIL

(Note 3)

1.0

Sleep Input Current, IIH

-25

+25

A

Electrical Specifications

AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued)

PARAMETER

TEST CONDITIONS

TA = -40oC TO 85oC

UNITS

MIN

TYP

MAX

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