TUSB564 datasheet(4/50 Pages) TI1

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TUSB564

SLLSF29C – OCTOBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: TUSB564

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Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

SSTXn

Diff I

Differential negative input for USB3.1 downstream facing port.

SSRXp

Diff O

Differential positive output for USB3.1 downstream facing port.

SSRXn

Diff O

Differential negative output for USB3.1 downstream facing port.

EQ1

4 Level I

This pin along with EQ0 sets the USB receiver equalizer gain for upstream facing RX1 and RX2

when USB used. Up to 11dB of EQ available.

EQ0

4 Level I

This pin along with EQ1 sets the USB receiver equalizer gain for upstream facing RX1 and RX2

when USB used. Up to 11 dB of EQ available.

Device Enable.

L = Device Disabled

H = Device Enabled

HPDIN

I/O

Hot Plug Detect. This pin is an input for Hot Plug Detect received from DisplayPort sink. When

HPDIN is Low for greater than 2ms, all DisplayPort lanes are disabled while the AUX to SBU

switch will remain closed.

I2C_EN

4 Level I

I2C Programming Mode or GPIO Programming Select. I2C is only disabled when this pin is ‘0".

0 = GPIO mode (I2C disabled)

R = TI Test Mode (I2C enabled at 3.3 V)

F = I2C enabled at 1.8 V

1 = I2C enabled at 3.3 V.

SBU1

I/O, CMOS

SBU1. This pin should be DC coupled to the SBU1 pin on the Type-C receptacle. A 2-M ohm

resistor to GND is also recommended.

SBU2

I/O, CMOS

SBU2. This pin should be DC coupled to the SBU2 pin on the Type-C receptacle. A 2-M ohm

resistor to GND is also recommended.

AUXp

I/O, CMOS

AUXp. DisplayPort AUX positive I/O connected to the DisplayPort sink through a AC coupling

capacitor. In addition to AC coupling capacitor, this pin also requires a 1M resistor to DP_PWR

(3.3 V). This pin along with AUXN is used by the TUSB564 for AUX snooping and is routed to

SBU1/2 based on the orientation of the Type-C.

AUXn

I/O, CMOS

AUXn. DisplayPort AUX negative I/O connected to the DisplayPort sink through a AC coupling

capacitor. In addition to AC coupling capacitor, this pin also requires a 1M resistor to GND. This

pin along with AUXP is used by the TUSB564 for AUX snooping and is routed to SBU1/2 based on

the orientation of the Type-C.

DPEQ1

4 Level I

DisplayPort Receiver EQ. This along with DPEQ0 will select the DisplayPort receiver equalization

gain.

DPEQ0/A1

4 Level I

DisplayPort Receiver EQ. This along with DPEQ1 will select the DisplayPort receiver equalization

gain. When I2C_EN is not ‘0’, this pin will also set the TUSB564 I2C address.

SSEQ1

4 Level I

Along with SSEQ0, sets the USB receiver equalizer gain for downstream facing SSTXP/N.

SSEQ0/A0

4 Level I

Along with SSEQ1, sets the USB receiver equalizer gain for downstream facing SSTXP/N. When

I2C_EN is not ‘0’, this pin will also set the TUSB564 I2C address.

FLIP/SCL

2 Level I

When I2C_EN=’0’ this is Flip control pin, otherwise this pin is I2C clock. . When used for I2C clock

pullup to I2C master's VCC I2C supply.

CTL0/SDA

2 Level I

When I2C_EN=’0’ this is a USB3.1 Switch control pin, otherwise this pin is I2C data. When used

for I2C data pullup to I2C master's VCC I2C supply.

CTL1

2 Level I

(Failsafe)

(PD)

DP Alt mode Switch Control Pin. When I2C_EN = ‘0’, this pin will enable or disable DisplayPort

functionality. Otherwise, when I2C_EN is not "0", DisplayPort functionality is enabled and disabled

through I2C registers.

L = DisplayPort Disabled.

H = DisplayPort Enabled.

VCC

6, 20, 28

3.3-V Power Supply

No connect pin. Leave open.

GND

Thermal Pad

Ground

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