CS5016 datasheet(12/40 Pages) CIRRUS

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during conversion much like a hold capacitor in a

sample/hold amplifier.

The conversion consists of manipulating the free

plates of the capacitor array to VREF and AGND

to form a capacitive divider. Since the charge at

the floating node remains fixed, the voltage at

that point depends on the proportion of capaci-

t ance ti ed to VR EF versus AGND. Th e

successive-approximation algorithm is used to

find the proportion of capacitance, termed D in

Figure 2b, which when connected to the refer-

ence will drive the voltage at the floating node

(Vfn) to zero. That binary fraction of capacitance

represents the converter’s digital output.

This charge redistribution architecture easily sup-

ports bipolar input ranges. If half the capacitor

array (the MSB capacitor) is tied to VREF rather

than AIN in the track mode, the input range is

doubled and is offset half-scale. The magnitude

of the reference voltage thus defines both positive

and negative full-scale (-VREF to +VREF), and

the digital code is an offset binary representation

of the input.

Calibration

The ability of the CS5012A/14/16 to convert ac-

curately clearly depends on the accuracy of their

comparator and DAC. The CS5012A/14/16 util-

ize an "auto-zeroing" scheme to null errors

introduced by the comparator. All offsets are

stored on the capacitor array while in the track

mode and are effectively subtracted from the in-

put signal when a conversion is initiated.

Auto-zeroing enhances power supply rejection at

frequencies well below the conversion rate.

To achieve complete accuracy from the DAC, the

CS5012A/14/16 use a novel self-calibration

scheme. Each bit capacitor, shown in Figure 1,

actually consists of several capacitors which can

be manipulated to adjust the overall bit weight.

An on-chip microcontroller adjusts the subarrays

to precisely ratio the bits. Each bit is adjusted to

just balance the sum of all less significant bits

plus one dummy LSB (for example, 16C = 8C +

4C + 2C + C + C). Calibration resolution for the

array is a small fraction of an LSB resulting in

nearly ideal differential and integral linearity.

DIGITAL CIRCUIT CONNECTIONS

The CS5012A/14/16 can be applied in a wide va-

riety of master clock, sampling, and calibration

conditions which directly affect the devices’ con-

version time and throughput. The devices also

feature on-chip 3-state output buffers and a com-

plete interface for connecting to 8-bit and 16-bit

digital systems. Output data is also available in

serial format.

Master Clock

The CS5012A/14/16 operate from a master clock

(CLKIN) which can be externally supplied or in-

ternally generated. The internal oscillator is

activated by externally tying the CLKIN input

low. Alternatively, the CS5012A/14/16 can be

synchronized to the external system by driving

the CLKIN pin with a TTL or CMOS clock sig-

nal.

CLKIN

Master Clock

(Optional)

HOLD

EOT

CS5012A/14/16

Figure 3b. Synchronous Sampling

CLKIN

Master Clock

(Optional)

HOLD

Sampling

Clock

CS5012A/14/16

Figure 3a. Asynchronous Sampling

CS5012A, CS5014, CS5016

2-18

DS14F8

CS5012A CS5014 CS5016

DS14F9

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