ISL68137IRAZ datasheet(21/54 Pages) RENESAS

21 / 54 page

ISL68137

FN8757 Rev.1.00

Page 21 of 54

Jun 26, 2017

Layout and Design Considerations

In addition to TB379, the following PCB layout and design

strategies are intended to minimize the noise coupling, the

impact of board parasitic impedances on converter performance,

and to optimize the heat dissipating capabilities of the printed

circuit board. This section highlights some important practices,

which should be followed during the layout process.

Table 4 provides general guidance on best practices related to

pin noise sensitivity. Use of good engineering judgment is

required to implement designs based on criteria specific to the

situation.

TABLE 4. PIN DESIGN AND/OR LAYOUT CONSIDERATIONS

NAME

NOISE

SENSITIVE

DESCRIPTION

VINSEN

Yes

Connects to the resistor divider between VIN and

GND (see Figure 17 on page 17). Filter VINSEN

with 10nF to GND.

RGNDx

VSENx

Yes

Treat each of the remote voltage sense pairs as

differential signals in the PCB layout. They

should be routed side by side on the same layer.

They should not be routed in proximity to noisy

signals like PWM or Phase. Tie to ground when

not used.

PGx

Open-drain. 3.3V maximum pull-up voltage. Tie

to ground when not used.

SCL, SDA,

SALRT

Yes

50kHz to 2MHz signal during communication,

pair up with SALRT and route carefully. 20 mils

spacing within SDA, SALRT, and SCL; and more

than 30 mils to all other signals. Refer to the

SMBus design guidelines and place proper

termination resistance for impedance

matching. Tie to ground when not used.

AVS_CLK,

AVS_SDA,

AVS_MDA

Yes

Up to 50MHz signals during communication,

route carefully. 20 mils spacing within CLK, SDA,

and MDA; and more than 30 mils to all other

signals. Tie CLK and MDA to ground when not

used.

TMONx

Yes

When diode sensing is used, VCCS is the return

path for the delta Vbe currents. Use a separate

VCCS route specifically for diode temp sense. A

filter capacitor no greater than 500pF should be

placed between each TMON pin and the VCCS

pin near the IC. Tie to ground when not used.

TWARN

Open-drain. 3.3V maximum pull-up voltage.

VCC

Yes

Place at least 2.2µF MLCC decoupling capacitor

directly at the pin.

VCCS

Yes

Place 4.7µF MLCC decoupling capacitor directly

at the pin.

PWM

Avoid routing near noise sensitive analog lines

such as current sense or voltage sense.

CSx

CSRTNx

Yes

Treat each of the current sense pairs as

differential signals in the PCB layout. They

should be routed side by side on the same layer.

They should not be routed in proximity to noisy

signals like PWM or Phase. Proper routing of

current sense is perhaps the most critical of all

the layout tasks. Tie to ground when not used.

GND

Yes

This EPAD is the return of PWM output drivers.

Use four or more vias to directly connect the

EPAD to the power ground plane.

General

Comments

The layer next to the top or bottom layer is

preferred to be ground layers, while the signal

layers can be sandwiched in the ground layers if

possible.

TABLE 4. PIN DESIGN AND/OR LAYOUT CONSIDERATIONS (Continued)

NAME

NOISE

SENSITIVE

DESCRIPTION

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