ISL68124IRAZ datasheet(16/46 Pages) RENESAS

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ISL68124

FN8796 Rev.2.00

Page 16 of 46

June 16, 2017

Fault Monitoring and Protection

The ISL68124 actively monitors temperature, input voltage, output

voltage, and output current to detect and report fault conditions.

Fault monitors trigger configurable protective measures to prevent

damage to a load. The power-good indicators, PG0/PG1, are

provided for linking to external system monitors.

A high level of flexibility is provided in the ISL68124 fault logic.

Faults can be enabled or disabled individually. Each fault type can

also be configured to either latch off or retry indefinitely.

Power-Good Signals

The PG0/PG1 pins are open-drain, power-good outputs that

indicate completion of the soft-start sequence and output

voltage of the associated rail within the expected regulation

range.

The PG pins can be associated or disassociated with a number of

the available fault types. This allows a system design to be tailored

for virtually any condition. In addition, these power-good

indicators will be pulled low when a fault (OCP or OVP) condition

or UV condition is detected on the associated rail.

Output Voltage Protection

Output voltage is measured at the load sensing points

differentially for regulation and the same measurement is used

for OVP and UVP. The fault thresholds are set using PMBus

commands. Figure 17 shows a simplified OVP/UVP block

diagram. The output voltage comparisons are done in the digital

domain.

The device responds to an output overvoltage condition by

disabling the output, declaring a fault, setting the SALRT pin,

setting the PG pin, and then pulsing the LFET until the output

voltage has dropped below the threshold. Similarly, the device

responds to an output undervoltage condition by disabling the

output, declaring a fault, setting the SALRT pin, and setting the

PG pin. The output will not restart until the EN pin is cycled

(unless the device is configured to retry).

In addition, the ISL68124 features open pin sensing protection to

detect an open of the output voltage sensing circuit. This open

pin is detected as an OVP condition, which suspends the

controller operation.

Output Current Protection

The ISL68124 offers a comprehensive overcurrent protection

scheme. Each phase is protected from both excessive peak

current and sustained current. In addition, the system is

protected from sustained total output overcurrent.

Figure 18 depicts a block diagram of the system total output

current protection scheme. In this scheme, the phase currents

are summed to form ISUM. ISUM is then fed to dual response

paths allowing the user to program separate LPF, threshold, and

response time. One path is intended to allow response more

quickly than the other path. With this system, the user can allow

high peak total current for a short time and a lower level of

current for a sustained time. Note that neither of these paths

affect PWM activity on a cycle-by-cycle basis. The characteristics

of each path are easily set in PowerNavigator.

In addition to total output current, the ISL68124 provides an

individual phase peak current limit that will act on PWM in a

cycle-by-cycle manner. This means that if a phase current is

detected to exceed the OC threshold, the phase PWM signal will

be inverted to move current away from the threshold. In addition

to limiting positive or negative peak current on a cycle-by-cycle

basis, individual phase OC can be configured to limit current

indefinitely or to declare a fault after a programmable number of

consecutive OC cycles. This feature is useful for applications

where a fault shutdown of the system would not be acceptable,

but, some ability to limit phase currents is desired. Figures 21

and 22 depict this operation. If configured for indefinite current

limit, the converter will act as a current source and VOUT will not

remain at its regulation point. It should be noted that in this case,

VOUT OV or UV protection action may occur, which could shut the

regulator down.

FIGURE 17. OVP, UVP COMPARATORS

RGNDx

VSENx

ADC

DIGITAL OV

COMPARATOR

THRESHOLD

DIGITAL UV

COMPARATOR

THRESHOLD

SoC

FIGURE 18. OCP FUNCTIONAL DIAGRAM

ISUM

TIMER

FAULT

BLOCK

FILTER

COMPARE

TIMER

ACT

FILTER

FAST SUM OC

LIMIT

DELAY

TIMER

FAULT

BLOCK

FILTER COMPARE

TIMER

ACT

FILTER

SLOW SUM OC

LIMIT

DELAY

TOTAL OUTPUT CURRENT FAULT

Switching

Period

Count

FAULT

BLOCK

COMPARE

COUNT

ACT

+PEAK

LIMIT

OCCOUNT

fsw clk

-PEAK

LIMIT

Pulse by

pulse

limit

May be set

for indefinite

limiting but

no fault

assertion

Switching

Period

Count

FAULT

BLOCK

COMPARE

COUNT

ACT

UCCOUNT

fsw clk

Pulse by

pulse

limit

PHASE PEAK CURRENT LIMITING AND FAULT

IPHASEn

NEGATIVE PEAK LIMITING

POSITIVE PEAK LIMITING

May be set

for indefinite

limiting but

no fault

assertion



PH1 Current

Synthesizer

PHn Current

Synthesizer

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