ISL9237

FN8723 Rev.5.00

Page 4 of 40

Nov 29, 2017

4

BOOT2

High-side MOSFET Q4 gate driver supply. Connect an MLCC capacitor across the BOOT2 pin and the PHASE2 pin. The

boot capacitor is charged through an internal boot diode connected from the VDDP pin to the BOOT2 pin when the

PHASE2 pin drops below VDDP minus the voltage drop across the internal boot diode.

5

UGATE2

High-side MOSFET Q4 gate drive.

6

PHASE2

Current return path for the high-side MOSFET Q4 gate drive. Connect this pin to the node consisting of the high-side

MOSFET Q4 source, the low-side MOSFET Q3 drain and the one terminal of the inductor.

7

LGATE2

Low-side MOSFET Q3 gate drive.

8

VDDP

Power supply for the gate drivers. Connect to VDD pin through a 4.7Ω resistor and connect a 1µF ceramic capacitor to

GND.

9

LGATE1

Low-side MOSFET Q2 gate drive.

10

PHASE1

Current return path for the high side MOSFET Q1 gate drive. Connect this pin to the node consisting of the high-side

MOSFET Q1 source, the low-side MOSFET Q2 drain and the input terminal of the inductor.

11

UGATE1

High-side MOSFET Q1 gate drive.

12

BOOT1

High-side MOSFET Q1 gate driver supply. Connect an MLCC capacitor across the BOOT1 pin and the PHASE1 pin. The

boot capacitor is charged through an internal boot diode connected from the VDDP pin to the BOOT1 pin when the

PHASE1 pin drops below VDDP minus the voltage drop across the internal boot diode.

13

ASGATE

Gate drive output to the P-channel adapter FET. The use of ASGATE FETs is optional, if not used, leave ASGATE pin

floating.

When ASGATE turns on, it is clamped 10V below ADP pin voltage.

14

CSIN

Adapter current sense “-” input.

15

CSIP

Adapter current sense “+” input. The modulator also uses this for sensing input voltage in forward mode and output

voltage in reverse mode.

16

ADP

Adapter input. Used to sense adapter voltage. When adapter voltage is higher than 3.2V, AGATE is turned on.

ADP pin is also one of the two internal low power LDO inputs.

17

DCIN

Input of an internal LDO; provides power to the IC. Connect a diode OR from adapter and system outputs. Bypass this

pin with an MLCC capacitor.

18

VDD

Output of the internal LDO; provides the bias power for the internal analog and digital circuit. Connect a 1µF ceramic

capacitor to GND.

If VDD is pulled below 2V for more than 1ms, ISL9237 will reset all the SMBus register values to the default.

19

ACIN

Adapter voltage sense. Use a resistor divider externally to detect adapter voltage. The adapter voltage is valid if the ACIN

pin voltage is greater than 0.8V.

20

OTGEN/

CMIN

OTG function enable pin or stand-alone comparator input pin.

Pull high to enable OTG function. The OTG function is enabled when the control register is written to select OTG mode

and when the battery voltage is above 5.8V.

When OTG function is not selected, this pin is the general purpose stand-alone comparator input.

21

SDA

SMBus data I/O. Connect to the data line from the host controller or smart battery. Connect a 10k pull-up resistor

according to SMBus specification.

22

SCL

SMBus clock I/O. Connect to the clock line from the host controller or smart battery. Connect a 10k pull-up resistor

according to SMBus specification.

23

PROCHOT#

Open-drain output. Pulled low when ACProchot#, DCProchot# or Low_VSYS event is detected. IMVP-8 compliant.

24

ACOK

Adapter presence indicator output to indicate the adapter is ready.

25

BATGONE

Input pin to the IC. Logic high on this pin indicates the battery has been removed. Logic low on this pin indicates the

battery is present.

BATGONE pin logic high will force BGATE FET to turn off in any circumstance.

26

OTGPG/

CMOUT

Open-drain output. OTG function output power-good indicator or the stand-alone comparator output.

When OTG function is enabled, low if OTG output voltage is not within regulation window.

When OTG function is not used, it is the general purpose comparator output.

PIN NUMBER

PIN NAME

DESCRIPTION