AM29BDS640G datasheet(35/65 Pages) SPANSION

35 / 65 page

October 1, 2003 25903C1

Am29BDS640G

Prelimin ary

in the standard program command sequence, resulting in faster total program-

ming time. The host system may also initiate the chip erase and sector erase

sequences in the unlock bypass mode. The erase command sequences are four

cycles in length instead of six cycles. Table 13, “Command Definitions,” on

page 37 shows the requirements for the unlock bypass command sequences.

During the unlock bypass mode, only the Unlock Bypass Program, Unlock Bypass

Sector Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset commands are

valid. To exit the unlock bypass mode, the system must issue the two-cycle un-

lock bypass reset command sequence. The first cycle must contain the bank

address and the data 90h. The second cycle need only contain the data 00h. The

bank then returns to the read mode.

The device offers accelerated program operations through the ACC input. When

the system asserts VID on this input, the device automatically enters the Unlock

Bypass mode. The system may then write the two-cycle Unlock Bypass program

command sequence. The device uses the higher voltage on the ACC input to ac-

celerate the operation.

Figure 2 illustrates the algorithm for the program operation. Refer to the Erase/

Program Operations table in the AC Characteristics section for parameters, and

Figure 21, “Asynchronous Program Operation Timings,” on page 59 for timing

diagrams.

Notes:

1. See Table 13 for erase command sequence.

2. See the section on DQ3 for information on the sector erase timer.

Figure 2. Erase Operation

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFh?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

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