ISL6719

FN6555 Rev 2.00

Page 8 of 9

July 15, 2014

Figure 6 depicts the transient response of VSW during a 10mA

to 100mA step load when AUXIN is set to 15V and VPWR is set

to 18V.

VPWR

VPWR provides the source voltage for the IC and load until

AUXIN is back biased. VSW is disabled and the IC operates in a

standby (low power consumption) mode when UVLO is active.

If the application requires high currents or longer start-up

times than the thermal protection allows, the device

dissipation may be reduced by adding a resistor or resistors in

series between the input voltage and VPWR. The dropping

resistance must be selected such that VPWR remains above

the UVLO threshold of VPWR and at least 6.2V greater than

VSW under maximum load and minimum input voltage to

maintain regulation.

ENABLE, ENABLE_N

The ENABLE and ENABLE_N are complementary inputs used to

turn VSW on and off. Both polarities of the enable function are

provided to ease the interface to the application. The VSW may

be enabled by either ENABLE or ENABLE_N, but both inputs

must be logically false to disable the output. Each enable input

has a nominal 100k

 pull-up resistor to 5V.

The inputs can accept voltages up to 6V maximum down to

0.3V below signal ground. Voltages beyond these limits,

including transients, may cause permanent damage to the

device. Care should be taken when connecting signal sources

through long connections or if significant ground shift could

occur between the source and the input. In such

circumstances, it is recommended that appropriate clamping

networks be used to prevent possible electrical overstress.

Over-Temperature Protection

The ISL6719 has an over-temperature shutdown mechanism

to protect the device from excessive dissipation. The VSW

shutdown occurs approximately at +150°C. The hysteresis is

large so that the IC has sufficient time to operate at start-up

loading levels without re-triggering the over-temperature

protection.

FIGURE 6. VSW TRANSIENT RESPONSE, 10mA TO 100mA STEP,

VPWR = 18V, AUXIN = 15V, VSW = 12V

TRACE 1: VSW

FIGURE 7. ADDING DROPPING RESISTORS TO VPWR

1

COMPB

2

5

7

8

9

3

4

6

COMPA

ENABLE

ENABLE

_N

GND

VPWR

AUXIN

VSW

VSW_FB

TABLE 1. ENABLE, ENABLE_N TRUTH TABLE

INPUTS

OUTPUT

ENABLE

ENABLE_N

VSW

00

ON

01

OFF

10

ON

11

ON