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TSA1401IF датащи(PDF) 16 Page - STMicroelectronics |
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TSA1401IF датащи(HTML) 16 Page - STMicroelectronics |
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16 / 19 page ![]() TSA1401 APPLICATION INFORMATION 16/19 - To keep the capacitive loading as low as possible at digital outputs, short lead lengths when routing are essential to minimize currents when the output changes. To minimize this output capacitance, buffers or latches close to the output pins can relax this constraint. It is also helpful to use 47 to 56 ohms series resistors at the ADC output pins, located as close to the ADC output pins as possible. - Choose component sizes as small as possible (SMD). EVAL1401 evaluation board The characterization of the board has been made with a fully ADC devoted test bench. The schematic of the evaluation board is shown on figure 19. The analog signal must be filtered to be very pure. The dataready signal is the acquisition clock of the logic analyzer. All characterization measurement has been made with an input amplitude of +0.2dB for static parameters and -0.5dB for dynamic parameters |
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