HIP6302

FN4766 Rev.3.00

Page 3 of 16

December 27, 2004

Simplified Power System Diagram

Functional Pin Description

VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4)

and VID0 (Pin 5)

Voltage Identification inputs from microprocessor. These pins

respond to TTL and 3.3V logic signals. The HIP6302 decodes

VID bits to establish the output voltage. See Table 1.

COMP (Pin 6)

Output of the internal error amplifier. Connect this pin to the

external feedback and compensation network.

FB (Pin 7)

Inverting input of the internal error amplifier.

FS/DIS (Pin 8)

this pin to ground sets the switching frequency of the

converter. Pulling this pin to ground disables the converter

and three states the PWM outputs. See Figure 10.

GND (Pin 9)

Bias and reference ground. All signals are referenced to this

pin.

VSEN (Pin 10)

Power good monitor input. Connect to the microprocessor-

CORE voltage.

ISEN2 (Pin 11) and ISEN1 (Pin 14)

Current sense inputs from the individual converter channel’s

phase nodes.

PWM2 (Pin 12) and PWM1 (Pin 13)

PWM outputs for each driven channel in use. Connect these

pins to the PWM input of a HIP6601/2/3 driver.

PGOOD (Pin 15)

Power good. This pin provides a logic-high signal when the

microprocessor CORE voltage (VSEN pin) is within specified

limits and Soft-Start has timed out.

Bias supply. Connect this pin to a 5V supply.

SYNCHRONOUS

HIP6302

MICROPROCESSOR

VSEN

VID

RECTIFIED BUCK

CHANNEL

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

PWM 1

PWM 2

VID4

VID3

VID2

VID1

VID0

FS/DIS

VSEN

PGOOD

PWM1

PWM2

FB

ISEN1

COMP

ISEN2

GND

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8