HIP6301

FN4765 Rev 6.00

Page 3 of 17

December 27, 2004

Simplified Power System Diagram

Functional Pin Description

VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4)

and VID0 (Pin 5)

Voltage Identification inputs from microprocessor. These pins

respond to TTL and 3.3V logic signals. The HIP6301 decodes

VID bits to establish the output voltage. See Table 1.

COMP (Pin 6)

Output of the internal error amplifier. Connect this pin to the

external feedback and compensation network.

FB (Pin 7)

Inverting input of the internal error amplifier.

FS/DIS (Pin 8)

this pin to ground sets the switching frequency of the

converter. Pulling this pin to ground disables the converter

and three states the PWM outputs. See Figure 10.

GND (Pin 9)

Bias and reference ground. All signals are referenced to this

pin.

VSEN (Pin 10)

Power good monitor input. Connect to the microprocessor-

CORE voltage.

PWM1 (Pin 15), PWM2 (Pin 14), PWM3 (Pin 11) and

PWM4 (Pin 18)

PWM outputs for each driven channel in use. Connect these

pins to the PWM input of a HIP6601B/2B/3B/4B driver. For

systems which use 3 channels, connect PWM4 high. Two

channel systems connect PWM3 and PWM4 high.

ISEN1 (Pin 16), ISEN2 (Pin 13), ISEN3 (Pin 12) and

ISEN4 (Pin 17)

Current sense inputs from the individual converter channel’s

phase nodes. Unused sense lines MUST be left open.

PGOOD (Pin 19)

Power good. This pin is an open-drain logic signal that

indicates when the microprocessor CORE voltage (VSEN

pin) is within specified limits and Soft-Start has timed out.

Bias supply. Connect this pin to a 5V supply.

SYNCHRONOUS

HIP6301

MICROPROCESSOR

VSEN

VID

RECTIFIED BUCK

CHANNEL

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

PWM 1

PWM 2

PWM 3

PWM 4

11

12

13

14

15

16

17

18

20

19

10

9

8

7

6

5

4

3

2

1

VID4

VID3

VID2

VID1

VID0

FS/DIS

PWM2

PGOOD

PWM3

ISEN4

ISEN1

GND

ISEN3

FB

PWM4

VSEN

COMP

PWM1

ISEN2