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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TLE6211 датащи(PDF) 24 Page - Infineon Technologies AG |
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TLE6211 датащи(HTML) 24 Page - Infineon Technologies AG |
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24 / 35 page  TLE 6210 TLE 6211 Block Description and Electrical Characteristics V1.2 Data Sheet 24 2002-08 The logic expects the time between two clock edges between 3 and 15 clock-cycles. If this window is not met, the outputs VR, MR and NSILA are switched off, SILA is switched on and the enable output goes low. An internal counter ( seeFigure 12) includes a 4 bit counter. Each time the value 15 is reached a dominant counter reset signal is generated at the output "=15". This pulse is generated continuously at t = (15+3) T1 + n * (16*T1) after the last valid watchdog pulse was detected. When internal resets and watchdog edges occur at the same time, the internal reset is dominant. Figure 7 Missing watchdog signals cause EN low 1 0 1 0 1 0 15* t CLK + Delay = 15* t CLK + 3* tCLK 10ms WD1 WD2 EN Delay (3* t CLK) t > 16 *t CLK wd-controls-en-2 AD 04/02 |
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