TAS5142 datasheet(10/26 Pages) TI

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ELECTRICAL CHARACTERISTICS

TAS5142

SLES126B – DECEMBER 2004 – REVISED MAY 2005

L= 4 Ω, FPWM = 384 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions

unless otherwise specified.

TAS5142

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

Internal Voltage Regulator and Current Consumption

Voltage regulator, only used as a

VREG

VDD = 12 V

3.3

3.6

reference node

Operating, 50% duty cycle

IVDD

VDD supply current

Idle, reset mode

50% duty cycle

IGVDD_X

Gate supply current per half-bridge

Reset mode

0.3

50% duty cycle, without output filter or load

IPVDD_X

Half-bridge idle current

Reset mode, no switching

µA

Output Stage MOSFETs

TJ = 25°C, includes metallization resistance,

RDSon,LS

Drain-to-source resistance, LS

140

155

Ω

GVDD = 12 V

TJ = 25°C, includes metallization resistance,

RDSon,HS

Drain-to-source resistance, HS

140

155

Ω

GVDD = 12 V

I/O Protection

Undervoltage protection limit,

Vuvp,G

9.8

GVDD_X

Vuvp,hyst(1)

250

OTW(1)

Overtemperature warning

115

125

135

°C

Temperature drop needed below

OTWHYST(1)

OTW temp. for OTW to be inactive

°C

after the OTW event

OTE(1)

Overtemperature error

145

155

165

°C

OTE-

OTE-OTW differential

°C

OTWdifferential(1)

A reset event must occur for SD to

OTEHYST(1)

°C

be released following an OTE event.

OLPC

Overload protection counter

FPWM = 384 kHz

1.25

Resistor—programmable, high-end,

IOC

Overcurrent limit protection

7.9

9.7

11.4

ROCP = 18 kΩ

IOCT

Overcurrent response time

210

ROCP

OC programming resistor range

Resistor tolerance = 5%

Ω

Connected when RESET is active to provide

Internal pulldown resistor at the out-

RPD

bootstrap capacitor charge. Not used in SE

2.5

Ω

put of each half-bridge

mode

Static Digital Specifications

VIH

High-level input voltage

PWM_A, PWM_B, PWM_C, PWM_D, M1,

M2, M3, RESET_AB, RESET_CD

VIL

Low-level input voltage

0.8

Leakage

Input leakage current

–10

µA

OTW/SHUTDOWN (SD)

Internal pullup resistance, OTW to

RINT_PU

Ω

VREG, SD to VREG

Internal pullup resistor

3.3

3.6

VOH

High-level output voltage

External pullup of 4.7 k

Ω to 5 V

4.5

VOL

Low-level output voltage

IO = 4 mA

0.2

0.4

FANOUT

Device fanout OTW, SD

No external pullup

Devices

(1)

Specified by design

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