FN6399 Rev 0.00

Page 10 of 11

March 21, 2007

ISL9212B

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voltage of the AC adapter. The actual peak voltage is

dependent on the damping factor that is mainly determined

by the parasitic resistance (R in Figure 25).

In practice, the input decoupling capacitor is recommended

to use a 16V X5R dielectric ceramic capacitor with a value

between 0.1µF to 1µF.

The output of the ISL9212B and the input of the charging

circuit typically share one decoupling capacitor. The

selection of that capacitor is mainly determined by the

requirement of the charging circuit. When using the ISL6292

family chargers, a 1µF, 6.3V, X5R capacitor is

recommended.

Layout Recommendation

The ISL9212B uses a thermally enhanced DFN package.

The exposed pad under the package should be connected to

the ground plane electrically as well as thermally. A grid of

1.0mm to 1.2mm pitch thermal vias in two rows and 4 to 5

vias per row is recommended (refer to the ISL9212BEVAL1

evaluation board layout). The vias should be about 0.3mm to

0.33mm in diameter. Use some copper on the component

layer if possible to further improve the thermal performance

but it is not mandatory.

Since the ISL9212B is a protection device, the layout should

also pay attention to the spacing between tracks. When the

distance between the edges of two tracks is less than

0.76mm, an FMEA (failure mechanism and effect analysis)

should be performed to ensure that a short between those

two tracks does not lead to the charger output exceeding the

“Lithium-Safe” region limits. Intersil will have the FMEA

document for the solution using the ISL9212B and the

ISL6292C chip set but the layout FMEA should be added as

part of the analysis.