ISL8014A

FN7525 Rev 2.00

Page 13 of 16

December 16, 2014

Synchronization Control

The frequency of operation can be synchronized up to 4MHz by an

external signal applied to the SYNCH pin. The falling edge on the

SYNCH triggers the rising edge of the LX pulse. Make sure that the

minimum on time of the LX node is greater than 140ns.

Overcurrent Protection

The overcurrent protection is realized by monitoring the CSA output

with the OCP comparator, as shown in the “Block Diagram”. The

current sensing circuit has a gain of 200mV/A, from the P-MOSFET

current to the CSA output. When the CSA output reaches 1.4V,

which is equivalent to 5.7A for the switch current, the OCP

comparator is tripped to turn off the P-MOSFET immediately. The

overcurrent function protects the switching converter from a shorted

output by monitoring the current flowing through the upper MOSFET.

Upon detection of overcurrent condition, the upper MOSFET will

be immediately turned off and will not be turned on again until

the next switching cycle. Upon detection of the initial overcurrent

condition, the overcurrent fault counter is set to 1. If, on the

subsequent cycle, another overcurrent condition is detected, the

OC fault counter will be incremented. If there are 17 sequential

OC fault detections, the regulator will be shut down under an

overcurrent fault condition. An overcurrent fault condition will

result in the regulator attempting to restart in a hiccup mode

within the delay of four soft-start periods. At the end of the fourth

soft-start wait period, the fault counters are reset and soft-start is

attempted again. If the overcurrent condition goes away during

the delay of four soft-start periods, the output will resume back

into regulation point after hiccup mode expires.

Short-Circuit Protection

The short-circuit protection SCP comparator monitors the VFB pin

voltage for output short-circuit protection. When the VFB is lower

than 0.2V, the SCP comparator forces the PWM oscillator

frequency to drop to 1/3 of the normal operation value. This

comparator is effective during start-up or an output short-circuit

event.

PG

During power-up, the open-drain power-good output holds low for

output also serves as a 1ms delayed the power-good signal when

UVLO

When the input voltage is below the undervoltage lockout (UVLO)

threshold, the regulator is disabled. To adjust the voltage level of

power on and UVLO, use a resistive divider across EN. The input

between 10kΩ and 100kΩ.

Soft Start-Up

The soft start-up reduces the inrush current during the start-up.

The soft-start block outputs a ramp reference to the input of the

error amplifier. This voltage ramp limits the inductor current as

well as the output voltage speed so that the output voltage rises

in a controlled fashion. When VFB is less than 0.2V at the

beginning of the soft-start, the switching frequency is reduced to

1/3 of the nominal value so that the output can start up

smoothly at light load condition. During soft-start, the IC operates

in the SKIP mode to support pre-biased output condition.

Enable

The enable (EN) input allows the user to control the turning on or

off the regulator for purposes such as power-up sequencing.

When the regulator is enabled, there is typically a 600µs delay

for waking up the bandgap reference and then the soft-start-up

begins. It is recommended that the EN voltage should be kept

rate.

such that the voltage is 1.4V (minimum enable logic high

Then select C such that the equivalent time constant is at least

2x the rise time, T. This will delay the EN voltage enough so that

reaches 2.5V. Use Equation 2 to get C:

R4

R5

1V

EN

FIGURE 36. EXTERNAL RESISTOR DIVIDER

C

VIN

EN

<400mV

2.5V

T

t (TIME)

–





1.4V

---------------------------------------------

=

(EQ. 1)

C

2T





--------------------



(EQ. 2)