2

PS8474

04/25/00

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PI74ALVC162835FD

18-Bit Universal Bus Driver with 3-State Outputs

s

t

u

p

n

I

s

t

u

p

t

u

O

Y

E

OE

LK

L

CA

H

XXX

Z

LH

X

L

L

LH

X

H

H

LL

↑

LL

LL

↑

HH

LL

H

X

o

(

LLL

X

o

(

Pin Name

Description

OE

Output Enable Input (Active LOW)

LE

Latch Enable

CLK

Clock Input

A

Data Input

Y

Data Output

GND

Ground

Power

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

25

26

27

28

32

31

30

29

Product Pin Description

Notes:

1. H = High Signal Level

L = Low Signal Level

Z = High Impedance

↑ = Transition LOW-to-HIGH

X = Irrelevant

2. Output level before the indicated steady-state input

conditions were established, provided that CLK is

high before LE goes low.

3. Output level before the indicated steady-state input

conditions were established.

Product Pin Configuration

GND

NC

A1

GND

A2

A3

VCC

A4

A5

A6

GND

A7

A8

A9

A10

A11

A12

GND

A13

A14

A15

VCC

A16

A17

GND

A18

CLK

GND

NC

NC

Y1

GND

Y2

Y3

VCC

Y4

Y5

Y6

GND

Y7

Y8

Y9

Y10

Y11

Y12

GND

Y13

Y14

Y15

VCC

Y16

Y17

GND

Y18

OE

LE

56-Pin

A,K,V