NT5DS32M8AT datasheet(21/27 Pages) ETC

21 / 27 page

NT5DS64M4AT NT5DS64M4AW

NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Preliminary

10/01

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC Input Operating Conditions (0 °C

≤ T

A ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC

Characteristics)

Symbol

Parameter/Condition

Min

Max

Unit

Notes

VIH(AC)

Input High (Logic 1) Voltage, DQ, DQS, and DM Signals

VREF + 0.31

1, 2

VIL(AC)

Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals

VREF − 0.31

1, 2

VID(AC)

Input Differential Voltage, CK and CK Inputs

0.62

VDDQ + 0.6

1, 2, 3

VIX(AC)

Input Crossing Point Voltage, CK and CK Inputs

0.5*VDDQ − 0.2 0.5*VDDQ + 0.2

1, 2, 4

1. Input slew rate = 1V/ns

2. Inputs are not recognized as valid until VREF stabilizes.

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.

IDD Specifications and Conditions (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC

Characteristics)

Symbol

Parameter/Condition

DDR333

tCK=6ns

DDR333

tCK=6.6ns

Unit

Notes

IDD0

Operating Current: one bank; active / precharge; tRC = tRC (min); DQ, DM, and

DQS inputs changing twice per clock cycle; address and control inputs changing

once per clock cycle

IDD1

Operating Current: one bank; active / read / precharge; Burst = 2; tRC = tRC

(min); CL = 2.5; IOUT = 0mA; address and control inputs changing once per clock

cycle

110

IDD2P

Precharge Power-Down Standby Current: all banks idle; power-down mode;

CKE

≤ V

IL (max)

IDD2N

Idle Standby Current: CS

≥ V

IH (min); all banks idle; CKE ≥ VIH (min);

address and control inputs changing once per clock cycle

IDD3P

Active Power-Down Standby Current: one bank active; power-down mode;

CKE

≤ V

IL (max)

IDD3N

Active Standby Current: one bank; active / precharge; CS

≥ V

IH (min);

CKE

≥ V

IH (min); tRC = tRAS (max); DQ, DM, and DQS inputs changing twice per

clock cycle; address and control inputs changing once per clock cycle

IDD4R

Operating Current: one bank; Burst = 2; reads; continuous burst; address and

control inputs changing once per clock cycle; DQ and DQS outputs changing

twice per clock cycle; CL = 2.5; IOUT = 0mA

165

IDD4W

Operating Current: one bank; Burst = 2; writes; continuous burst; address and

control inputs changing once per clock cycle; DQ and DQS inputs changing twice

per clock cycle; CL = 2.5

150

IDD5

Auto-Refresh Current: tRC = tRFC (min)

170

IDD6

Self-Refresh Current: CKE

≤ 0.2V

1, 2

IDD7

Operating current: four bank; four bank interleaving with BL = 4, address and

control inputs randomly changing; 50% of data changing at every transfer;

t RC = t RC (min); I OUT = 0mA.

150

1. IDD specifications are tested after the device is properly initialized.

2. Enables on-chip refresh and address counters.

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