K64F datasheet(58/85 Pages) NXP

58 / 85 page

Table 47. Slave mode DSPI timing (full voltage range) (continued)

Num

Description

Min.

Max.

Unit

Frequency of operation

—

7.5

MHz

DS9

DSPI_SCK input cycle time

8 x tBUS

—

DS10

DSPI_SCK input high/low time

(tSCK/2) - 4

(tSCK/2) + 4

DS11

DSPI_SCK to DSPI_SOUT valid

—

23.5

DS12

DSPI_SCK to DSPI_SOUT invalid

—

DS13

DSPI_SIN to DSPI_SCK input setup

—

DS14

DSPI_SCK to DSPI_SIN input hold

—

DS15

DSPI_SS active to DSPI_SOUT driven

—

DS16

DSPI_SS inactive to DSPI_SOUT not driven

—

First data

Last data

First data

Data

Last data

Data

DS15

DS10

DS9

DS16

DS11

DS12

DS14

DS13

DSPI_SS

DSPI_SCK

(CPOL=0)

DSPI_SOUT

DSPI_SIN

Figure 28. DSPI classic SPI timing — slave mode

3.8.8 Inter-Integrated Circuit Interface (I2C) timing

Table 48. I 2C timing

Characteristic

Symbol

Standard Mode

Fast Mode

Unit

Minimum

Maximum

Minimum

Maximum

SCL Clock Frequency

fSCL

100

4001

kHz

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated.

tHD; STA

—

0.6

—

µs

LOW period of the SCL clock

tLOW

4.7

—

1.25

—

µs

HIGH period of the SCL clock

tHIGH

—

0.6

—

µs

Set-up time for a repeated START

condition

tSU; STA

4.7

—

0.6

—

µs

Data hold time for I2C bus devices

tHD; DAT

3.453

0.92

µs

Table continues on the next page...

Peripheral operating requirements and behaviors

Kinetis K64F Sub-Family Data Sheet, Rev. 7, 11/2016

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