HIP6019B

FN4587 Rev 1.00

Page 13 of 15

April 13, 2005

current value to the post-transient current level. During this

interval the difference between the inductor current and the

transient current level must be supplied by the output

capacitors. Minimizing the response time can minimize the

output capacitance required.

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

application and removal of a transient load:

response time to the removal of load. With a +5V input

source, the worst case response time can be either at the

application or removal of load and dependent upon the

output voltage setting. Be sure to check both of these

equations at the minimum and maximum output levels for

the worst case response time.

Input Capacitor Selection

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select the bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum

input voltage and a voltage rating of 1.5 times is a

conservative guideline.

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use ceramic capacitance

for the high frequency decoupling and bulk capacitors to

supply the RMS current. Small ceramic capacitors should be

placed very close to the upper MOSFET to suppress the

voltage induced in the parasitic circuit impedances.

For a through hole design, several electrolytic capacitors

(Panasonic HFQ series or Nichicon PL series or Sanyo MV-

GX or equivalent) may be needed. For surface mount

designs, solid tantalum capacitors can be used, but caution

must be exercised with regard to the capacitor surge current

rating. These capacitors must be capable of handling the

surge-current at power-up. The TPS series available from

AVX, and the 593D series from Sprague are both surge

current tested.

MOSFET Selection/Considerations

The HIP6019B requires 4 N-Channel power MOSFETs. Two

MOSFETs are used in the synchronous-rectified buck

topology of PWM1 converter. PWM2 converter uses a

MOSFET as the buck switch and the linear controller drives

a MOSFET as a pass transistor. These should be selected

management requirements.

PWM1 MOSFET Selection and Considerations

In high-current PWM applications, the MOSFET power

dissipation, package selection and heatsink are the

dominant design factors. The power dissipation includes two

loss components; conduction loss and switching loss. These

losses are distributed between the upper and lower

MOSFETs according to duty factor (see the equations

below). The conduction losses are the only component of

power dissipation for the lower MOSFETs. Only the upper

MOSFET has switching losses, since the lower device turns

on into near zero voltage.

The equations below assume linear voltage-current

transitions and do not model power loss due to the reverse-

recovery of the lower MOSFET’s body diode. The gate-

charge losses are proportional to the switching frequency

contributing to the MOSFETs’ temperature rise. However,

which increases the upper MOSFET switching losses.

Ensure that both MOSFETs are within their maximum

junction temperature at high ambient temperature by

calculating the temperature rise according to package

thermal resistance specifications. A separate heatsink may

be necessary depending upon MOSFET power, package

type, ambient temperature and air flow.

if the type device is used for both. This is because the gate

drive applied to the upper MOSFET is different than the

lower MOSFET. Figure 14 shows the gate drive where the

the gate-to-source voltage of Q1 is 7V. The lower gate drive

for Q1 and a logic-level MOSFET can be used for Q2 if its

absolute gate-to-source voltage rating exceeds the

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