TLF5303

January 1988

MM54HC75MM74HC75

4-Bit Bistable Latch with Q and Q Output

General Description

This 4-bit latch utilizes advanced silicon-gate CMOS tech-

nology to achieve the high noise immunity and low power

consumption normally associated with standard CMOS inte-

grated circuits These devices can drive 10 LS-TTL loads

This latch is ideally suited for use as temporary storage for

binary information processing inputoutput and indicator

units Information present at the data (D) input is transferred

to the Q output when the enable (G) is high The Q output

will follow the data input as long as the enable remains high

When the enable goes low the information that was present

at the data input at the time the transition occurred is re-

tained at the Q output until the enable is permitted to go

high again

The 54HC74HC logic family is functionally as well as pin-

out compatible with the standard 54LS74LS logic family

All inputs are protected from damage due to static dis-

Features

Y

Typical operating frequency 50 MHz

Y

Typical propagation delay 12 ns

Y

Wide operating supply voltage range 2 – 6V

Y

Low input current 1 mA maximum

Y

Low quiescent supply current 80 mA maximum

(74HC Series)

Y

Fanout of 10 LS-TTL loads

Connection and Logic Diagrams

Dual-In-Line Package

TLF5303 – 1

Order Number MM54HC75 or MM74HC75

Truth Table

Inputs

Outputs

DG

Q

Q

LH

L

H

HH

H

L

XL

(1 of 4 latches)

TLF5303 – 2

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A