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LT6204 датащи(PDF) 12 Page - Linear Technology |
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LT6204 датащи(HTML) 12 Page - Linear Technology |
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12 / 18 page ![]() LTC6253-7 12 62537f For more information www.linear.com/LTC6253-7 APPLICATIONS INFORMATION Circuit Description The LTC6253-7 has an input and output signal range that extends from the negative power supply to the positive power supply. Figure 1 depicts a simplified schematic of the amplifier. The input stage is comprised of two differ- ential amplifiers, a PNP stage, Q1/Q2, and an NPN stage, Q3/Q4 that are active over different common mode input voltages. The PNP stage is active between the negative supply to nominally 1.2V below the positive supply. As the inputvoltageapproachesthepositivesupply,thetransistor Q5 will steer the tail current, I1, to the current mirror, Q6/ Q7, activating the NPN differential pair and the PNP pair becomes inactive for the remaining input common mode range. Also, at the input stage, devices Q17 to Q19 act to cancel the bias current of the PNP input pair. When Q1/Q2 are active, the current in Q16 is controlled to be the same as the current in Q1 and Q2. Thus, the base current of Q16 is nominally equal to the base current of the input devices. The base current of Q16 is then mirrored by devices Q17 to Q19 to cancel the base current of the input devices Q1/ Q2.Apairofcomplementarycommonemitterstages,Q14/ Q15, enable the output to swing from rail-to-rail. Figure 1. LTC6253-7 Simplified Schematic Diagram –IN: Inverting Input of Amplifier. Input range from V– to V+. +IN: Non-Inverting Input of Amplifier. Input range from V– to V+. V+ : Positive Supply Voltage. Total supply voltage ranges from 2.5V to 5.25V. V–:NegativeSupplyVoltage.Typically0V.Thiscanbemade a negative voltage as long as 2.5V ≤ (V+ – V–) ≤ 5.25V. SHDN: Active Low Shutdown. Threshold is typically 1.1V referenced to V–. Floating this pin will turn the part on. OUT:AmplifierOutput.Swingsrail-to-railandcantypically source/sink over 90mA of current at a total supply of 5V. PIN FUNCTIONS 625234 F01 Q15 ESDD5 Q14 BUFFER AND OUTPUT BIAS R5 R4 Q13 Q12 I3 V– + Q8 R3 Q11 Q9 Q10 R2 R1 Q2 Q1 Q3 Q4 I1 + I2 + VBIAS Q5 Q6 Q19 Q7 D8 D7 Q18 Q17 D6 D5 ESDD2 V– ESDD1 V+ ESDD4 V– ESDD3 V+ Q16 V– V+ +IN –IN ESDD6 OUT |
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