LTC2602 datasheet(21/26 Pages) LINER

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LTC2311-16

231116fa

For more information www.linear.com/LTC2311-16

APPLICATIONS INFORMATION

TIMING AND CONTROL

CNV Timing

The LTC2311-16 sampling and conversion is controlled

by CNV. A rising edge on CNV will start sampling and the

fallingedgestartstheconversionandreadoutprocess.The

conversion process is timed by the SCK input clock. For

optimum performance, CNV should be driven by a clean

low jitter signal. The Typical Application at the back of the

data sheet illustrates a recommended implementation to

reduce the relatively large jitter from an FPGA CNV pulse

source.Notethelowjitterinputclocktimesthefallingedge

of the CNV signal. The rising edge jitter of CNV is much

less critical to performance. The typical pulse width of the

CNV signal is 30ns at a 5Msps conversion rate.

SCK Serial Data Clock Input

The falling edge of this clock shifts the conversion result

MSBfirstontotheSDOpins.A105MHzexternalclockmust

be applied at the SCK pin to achieve 5Msps throughput.

Nap/Sleep Modes

Nap mode is a method to save power without sacrificing

power-up delays for subsequent conversions. Sleep mode

has substantial power savings, but a power-up delay is

incurred to allow the reference and power systems to

become valid. To enter nap mode on the LTC2311-16,

the SCK signal must be held high or low and a series of

two CNV pulses must be applied. This is the case for both

CMOS and LVDS modes. The second rising edge of CNV

initiates the nap state. The nap state will persist until either

asinglerisingedgeofSCKisapplied,orfurtherCNVpulses

are applied. The SCK rising edge will put the LTC2311-16

back into the operational (full-power) state. When in nap

mode, two additional pulses will put the LTC2311-16 in

sleep mode. When configured for CMOS I/O operation, a

single rising edge of SCK can return the LTC2311-16 into

operational mode. A 10ms delay is necessary after exiting

sleep mode to allow the reference buffer to recharge the

external filter capacitor. In LVDS mode, exit sleep mode

by supplying a fifth CNV pulse. The fifth pulse will return

the LTC2311-16 to operational mode, and further SCK

pulses will keep the part from re-entering nap and sleep

modes. The fifth SCK pulse also works in CMOS mode

as a method to exit sleep. In the absence of SCK pulses,

repetitive CNV pulses will cycle the LTC2311-16 between

operational, nap and sleep modes indefinitely.

RefertothetimingdiagramsinFigure18,Figure19,Figure20

and Figure 21 for more detailed timing information about

sleep and nap modes.

Figure 18. CMOS and LVDS Mode NAP and WAKE Using SCK

FULL POWER MODE

CNV

SCK

HOLD STATIC HIGH OR LOW

NAP MODE

SDO

WAKE ON 1ST SCK EDGE

231116 F18

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