LTC3260 datasheet(13/22 Pages) LINER

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LT3095

3095fa

For more information www.linear.com/LT3095

tor. As an example, the loop bandwidth driving a 50mA

load with COUT = 2.2µF is about 1MHz. With such a high

bandwidth, the parasitic series resistance and inductance

of the output capacitor can have a noticeable impact on the

loop dynamics near the unity gain frequency. If the phase

response of the loop is degraded, transient output ringing

can result and supply ripple rejection may suffer. Avoid

these problems by using ceramic capacitors with ESR less

than 100mΩ; place the capacitor as close as possible to

the OUT pin and return directly to the adjacent GND pin.

See the discussion of board layout below for an example

PCB design that meets these requirements.

If capacitor types with higher ESR (>100 mΩ) or lower

self-resonantfrequencies(<500kHz) mustbeused,itmay

be necessary to parallel several output capacitors. This

lowers the effective ESR and ESL and can have beneficial

effects on ripple rejection.

Using an output capacitor with a value greater than the

minimum 2.2µF can improve ripple rejection under certain

conditions, as shown in the Typical Performance plots.

However, due to limitations in parasitic electromagnetic

coupling, the advantages may not be dramatic in practice.

A value of 2.2µF is recommended for most applications.

SET Pin (Reference Bypass) Capacitance

Within the bandwidth of the linear regulator, wideband

thermal noise and injected ripple at the output of the

LT3095’s built-in reference (that is, the SET pin) are

replicated at the output. Minimize this source of noise

by using an external capacitor to bypass the SET pin.

Table 1 shows the total RMS output noise in a 10Hz to

100kHz bandwidth and a 1kHz to 20MHz bandwidth for

several different values of CSET in a typical application.

The lower-bandwidth measurement reflects thermal and

shotnoiseonly, whilethehigher-bandwidthmeasurement

includes residual ripple components from the switch-

ing converter. Both are influenced by the value of CSET.

A minimum of 10nF is required, but noise is reduced

substantially with CSET ≥ 100nF.

APPLICATIONS INFORMATION

Table 1. Output Noise for Different Values of CSET

CSET

VOUT-AC

(µVRMS 10Hz to 100kHz)

VOUT-AC

(µVRMS 1kHz to 20MHz)

10nF

47nF

100nF

470nF

1µF

Single channel operation, VIN = 5V, VOUT = 18V, ILOAD = 50mA,

COUT = 2.2µF, CBSTOUT = 10µF

A system level consideration that may limit the value

of CSET is start-up time: when the part is enabled from

shutdown, the SET pin voltage rises with a time constant

of RSET • CSET. Since OUT tracks SET, this causes the

linear regulator output to soft-start. If very fast startup is

required and noise performance cannot be compromised,

use an auxiliary circuit to speed up the start time or drive

the SET pin externally (see Typical Applications).

Effective Operating Capacitance

The effective capacitance of a multilayer ceramic capacitor

varies over temperature and DC bias conditions, and may

be considerably lower than the manufacturer’s nominal

value. To ensure stable operation of the LT3095, make

sure that the boost and linear regulator output capacitors

meet the minimum requirement in their actual operating

conditions, after accounting for temperature and DC bias.

ALL CAPACITORS X5R, 25V RATING

0805

1206

1210

DC BIAS VOLTAGE (V)

3095 F02

Figure 2. Capacitance Degradation with DC Bias Voltage

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