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LT3045-1

30451fa

For more information www.linear.com/LT3045-1

APPLICATIONS INFORMATION

Minimize board leakage by encircling the SET pin with a

guard ring operated at a potential close to itself — ideally

tied to the OUT pin. Guarding both sides of the circuit

board is recommended. Bulk leakage reduction depends

on the guard ring width. Leakages of 100nA into or out of

the SET pin creates a 0.1% error in the reference voltage.

Leakages of this magnitude, coupled with other sources

of leakage, can cause significant errors in the output volt-

age, especially over wide operating temperature range.

Figure 2 illustrates a typical guard ring layout technique.

Figure 2. DFN Guard Ring Layout

Figure 3, minimize the effects of PCB trace and solder

inductance by tying the OUTS pin directly to COUT and

the GND side of CSET directly to the GND side of COUT,

as well as keep the GND sides of CIN and COUT reasonably

close. Refer to the LT3045-1 demo board manual for more

information on the recommended layout that meets these

requirements. While the LT3045-1 is robust enough not

to oscillate if the recommended layout is not followed,

depending on the actual layout, phase/gain margin, noise

and PSRR performance may degrade.

Stability and Output Capacitance

The LT3045-1 requires an output capacitor for stability.

Given its high bandwidth, LTC recommends low ESR and

ESL ceramic capacitors. A minimum 10µF output capaci-

tance with an ESR below 20mΩ and an ESL below 2nH is

required for stability.

Given the high PSRR and low noise performance attained

using a single 10µF ceramic output capacitor, larger values

of output capacitor only marginally improves the perfor-

mance because the regulator bandwidth decreases with

increasing output capacitance — hence, there is little to

be gained by using larger than the minimum 10µF output

capacitor.Nonetheless,largervaluesofoutputcapacitance

dodecreasepeakoutputdeviationsduringaloadtransient.

Note that bypass capacitors used to decouple individual

components powered by the LT3045-1 increase the ef-

fective output capacitance.

Figure 3. COUT and CSET Connections for Best Performance

30451 F02

OUT

SET

Since the SET pin is a high impedance node, unwanted

signals may couple into the SET pin and cause erratic

behavior. This is most noticeable when operating with a

minimum output capacitor at heavy load currents. By-

passing the SET pin with a small capacitance to ground

resolves this issue — 10nF is sufficient.

For applications requiring higher accuracy or an adjust-

able output voltage, the SET pin may be actively driven

by an external voltage source capable of sinking 100µA.

Connecting a precision voltage reference to the SET pin

eliminates any errors present in the output voltage due

to the reference current and SET pin resistor tolerances.

Output Sensing and Stability

The LT3045-1’s OUTS pin provides a Kelvin sense con-

nection to the output. The SET pin resistor’s GND side

provides a Kelvin sense connection to the load’s GND side.

Additionally, for ultrahigh PSRR, the LT3045-1 bandwidth

is made quite high (~1MHz), making it very close to a

typical 10µF (1206 case size) ceramic output capacitor’s

self-resonance frequency (~1.6MHz). Therefore, it is very

important to avoid adding extra impedance (ESR and

ESL) outside the feedback loop. To that end, as shown in

COUT

RSET

CSET

CIN

OUT

SET

VIOC

LT3045-1

DEMO BOARD

PCB LAYOUT

ILLUSTRATES

4-TERMINAL

CONNECTION

TO COUT

100µA

OUTS

ILIM

30451 F03

GND

PGFB

EN/UV

VOUT

IOUT(MAX): 500mA

VIN

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