Features and Operation

POWER DOWN/OFF

The device may be powered by its PD* pin. A Low on this pin

will power down the entire device.

TABLE 2. Power Down Output States

Mode

Pin

Type

Output State

in Power Down

SER

WCLKIO

LVCMOS

LOW

SER

MC

MPL

OFF

SER

MD

MPL

OFF

DES

D[0:7]

LVCMOS

LOW

DES

V, H

LVCMOS

LOW

DES

PCLK

LVCMOS

LOW

DES

WC

MPL

OFF

UN-USED/OPEN INPUTS

Un-used control/inputs pins must be driven to their appropri-

ate logic states to set up the desired operating modes.

UN-USED OUTPUTS

Unused outputs should be left open to minimize power dis-

sipation.

POWERING UP

The LM2501 should be powered up with all power supplies

at the same time, alternately VDDIO may lag VDD and

VDDA. Do not power up with VDDIO before VDD and VDDA.

PHASE-LOCKED LOOP

When the device is configured as a Serializer, a PLL is

provided to generate the serial link clock. The Phase-locked

loop system generates the serial data clock at five times the

input clock. The PLL operates with an input clock between

4 MHz and 16 MHz. The Deserializer does not utilize the PLL

and its PLL is powered down.

RESET

PD* should be held Low until the power supply has powered

up and is stable. The PD* should then be de-asserted to

generate a RESET and start up. Stopping the WCLKIO or

the PCLK will not RESET the part. A power cycle or PD*

cycle is requested to generate a RESET event.

SERIALIZER/DESERIALIZER SELECTION

The Mode[1:0] pins are used to configure the device as

either a Serializer or Deserializer and other configuration

options.

WHISPERCLOCK

An additional clock signal is sent from the Deserializer to the

Serializer. This can be used to pass a clock reference

(4 MHz to 28 MHz) up to the Camera device from the host.

This link is independent of the Serial data path (opposite

direction). See also Figure 5. The SER can only start up, if

the WCLKIO(ser-out) has been active.

20091608

FIGURE 10. Sleep to Active

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