LTC7813 datasheet(13/32 Pages) LINER

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LTC7800

7800f

For more information www.linear.com/LTC7800

A phase-locked loop (PLL) is available on the LTC7800

to synchronize the internal oscillator to an external clock

source that is connected to the PLLIN/MODE pin. The

LTC7800’s phase detector adjusts the voltage (through

an internal lowpass filter) of the VCO input to align the

turn-on of the controller’s external top MOSFET to the

rising edge of the synchronizing signal.

The VCO input voltage is prebiased to the operating fre-

quency set by the FREQ pin before the external clock is

applied. If prebiased near the external clock frequency,

the PLL loop only needs to make slight changes to the

VCO input in order to synchronize the rising edge of the

external clock’s to the rising edge of TG. The ability to

prebias the loop filter allows the PLL to lock-in rapidly

without deviating far from the desired frequency.

The typical capture range of the phase-locked loop is from

approximately 300kHz to 2.3MHz, with a guarantee to be

between 320kHz and 2.25MHz. In other words, the

LTC7800’s PLL is guaranteed to lock to an external clock

sourcewhosefrequencyisbetween320kHzand2.25MHz.

The typical input clock thresholds on the PLLIN/MODE

pin are 1.6V (rising) and 1.1V (falling). The LTC7800 is

guaranteed to synchronize to an external clock that swings

up to at least 2.5V and down to 0.5V or less.

Output Overvoltage Protection

An overvoltage comparator guards against transient over-

shoots as well as other more serious conditions that may

overvoltage the output. When the VFB pin rises by more

than 10% above its regulation point of 0.800V, the top

MOSFET is turned off and the bottom MOSFET is turned

on until the overvoltage condition is cleared.

Power Good Pin

ThePGOODpinisconnectedtoanopendrainofaninternal

N-channel MOSFET. The MOSFET turns on and pulls the

PGOOD pin low when the VFB pin voltage is not within

±10%ofthe0.8Vreferencevoltage.ThePGOODpinisalso

pulled low when the RUN pin is low (shut down). When

the VFB pin voltage is within the ±10% requirement, the

MOSFET is turned off and the pin is allowed to be pulled

up by an external resistor to a source no greater than 6V.

Foldback Current

When the output voltage falls to less than 70% of its

nominal level, foldback current limiting is activated, pro-

gressively lowering the peak current limit in proportion to

the severity of the overcurrent or short-circuit condition.

Foldback current limiting is disabled during the soft-start

interval (as long as the VFB voltage is keeping up with the

TRACK/SS voltage).

OPERATION

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