LTC7813 datasheet(22/38 Pages) LINER

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LTC3895

3895fa

For more information www.linear.com/LTC3895

The SS pin also controls the timing of the regulator

shutdown (REGSD) feature (as discussed in Regulator

ShutdownoftheOperationsection).Iftheapplicationdoes

not require the use of the EXTVCC LDO (the EXTVCC pin

is grounded), the REGSD feature must be defeated with

a pull-up resistor between SS and INTVCC, as shown in

Figure 7. Any resistor 330k or smaller between SS and

INTVCC defeats the 5μA pull-down current on SS that

turns on once SS reaches 2.2V (with the EXTVCC LDO

not enabled), preventing SS from discharging to 2.0V

and shutting down the regulator. Note the current through

this pull-up resistor adds to the internal 10μA SS pull-up

current at start-up, causing the total soft-start time to

be shorter than what it is calculated without the pull-up

resistor. The total soft-start time with the pull-up resistor

is approximately:

tSS ≈ CSS •

0.8V

10µA +

4.6V

RSS

⎛

⎝

⎜

⎞

⎠

⎟

where RSS is the value of the resistor between the SS and

INTVCC pins.

applicaTions inForMaTion

Figure 6. Using the SS Pin to Program Soft-Start

3895 F06

LTC3895

GND

CSS

Figure 7. Using the SS Pin to Program Soft-Start

with EXTVCC Unused/Grounded to Defeat REGSD

3895 F07

LTC3895

GND

INTVCC

EXTVCC

CSS

RSS

DRVCC Regulators (OPTI-DRIVE)

The LTC3895 features three separate low dropout linear

regulators (LDO) that can supply power at the DRVCC pin.

TheinternalVINLDOusesaninternalP-channelpassdevice

between the VINandDRVCCpins.TheinternalEXTVCCLDO

usesaninternalP-channelpassdevicebetweentheEXTVCC

and DRVCC pins. The NDRV LDO utilizes the NDRV pin to

drive the gate of an external N-channel MOSFET acting as

a linear regulator with its drain connected to VIN.

The NDRV LDO provides an alternative method to supply

power to DRVCC from the input supply without dissipating

the power inside the LTC3895 IC. It has an internal charge

pump that allows NDRV to be driven above the VIN sup-

ply, allowing for low dropout performance. The VIN LDO

has a slightly lower regulation point than the NDRV LDO,

such that all DRVCC current flows through the external N-

channel MOSFET (and not through the internal P-channel

pass device) once DRVCC reaches regulation.

When laying out the PC board, care should be taken to

route NDRV away from any switching nodes, especially

SW, TG, and BOOST. Coupling to the NDRV node could

cause its voltage to collapse and the NDRV LDO to lose

regulation. If this occurs, the internal VIN LDO would

take over and maintain DRVCC voltage at a slightly lower

regulation point. However, internal heating of the IC would

become a concern. High frequency noise on the drain of

the external NFET could also couple into the NDRV node

(through the gate-to-drain capacitance of the NDRV NFET)

and adversely affect NDRV regulation. The following are

methods that could mitigate this potential issue (refer to

Figure 8a).

1. Add local decoupling capacitors right next to the drain

of the external NDRV NFET in the PCB layout.

2. Insert a resistor (~100Ω) in series with the gate of the

NDRV NFET.

3. Insert a small capacitor (~1nF) between the gate and

source of the NDRV NFET.

When testing the application circuit, be sure the NDRV

voltage does not collapse over the entire input voltage

and output current operating range of the buck regulator.

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