LT8705 datasheet(24/38 Pages) LINER

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LTC3784

3784fb

For more information www.linear.com/LTC3784

applicaTions inForMaTion

Since the shutdown may occur at full load, beware that

the load current will result in high power dissipation in the

body diodes of the top MOSFETs. In this case, the PGOOD

output may be used to turn the system load off.

Phase-Locked Loop and Frequency Synchronization

The LTC3784 has an internal phase-locked loop (PLL)

comprised of a phase frequency detector, a lowpass filter

and a voltage-controlled oscillator (VCO). This allows the

turn-on of the bottom MOSFET of channel 1 to be locked

to the rising edge of an external clock signal applied to

the PLLIN/MODE pin. The turn-on of channel 2’s bottom

MOSFETisthus180degreesout-of-phasewiththeexternal

clock. The phase detector is an edge-sensitive digital type

thatprovideszerodegreesphaseshiftbetweentheexternal

and internal oscillators. This type of phase detector does

not exhibit false lock to harmonics of the external clock.

If the external clock frequency is greater than the internal

oscillator’sfrequency,fOSC,thencurrentissourcedcontinu-

ously from the phase detector output, pulling up the VCO

input. When the external clock frequency is less than fOSC,

current is sunk continuously, pulling down the VCO input.

If the external and internal frequencies are the same but

exhibit a phase difference, the current sources turn on for

an amount of time corresponding to the phase difference.

The voltage at the VCO input is adjusted until the phase

and frequency of the internal and external oscillators are

identical. At the stable operating point, the phase detector

output is high impedance and the internal filter capacitor,

CLP , holds the voltage at the VCO input.

Typically,theexternalclock(onthePLLIN/MODEpin)input

highthresholdis1.6V,whiletheinputlowthresholdis1.2V.

Note that the LTC3784 can only be synchronized to an

external clock whose frequency is within range of the

LTC3784’s internal VCO, which is nominally 55kHz to

1MHz.Thisisguaranteedtobebetween75kHzand850kHz.

RapidphaselockingcanbeachievedbyusingtheFREQpin

to set a free-running frequency near the desired synchro-

nization frequency. The VCO’s input voltage is prebiased

at a frequency corresponding to the frequency set by the

FREQ pin. Once prebiased, the PLL only needs to adjust

the frequency slightly to achieve phase lock and synchro-

nization. Although it is not required that the free-running

frequency be near external clock frequency, doing so will

prevent the operating frequency from passing through a

large range of frequencies as the PLL locks.

Figure 7. Relationship Between Oscillator

Frequency and Resistor Value at the FREQ Pin

FREQ PIN RESISTOR (k)

600

800

1000

35 45 55

3784 F07

400

200

500

700

900

300

100

65 75 85 95 105 115 125

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