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LTC3852

3852f

APPLICATIONS INFORMATION

Phase-Locked Loop and Frequency Synchronization

The LTC3852 has a phase-locked loop (PLL) comprised of

an internal voltage-controlled oscillator (VCO) and a phase

detector. This allows the turn-on of the top MOSFET to

be locked to the rising edge of an external clock signal

applied to the MODE/PLLIN pin. This phase detector is

an edge sensitive digital type that provides zero degrees

phase shift between the external and internal oscillators.

This type of phase detector does not exhibit false lock to

harmonics of the external clock.

The output of the phase detector is a pair of complementary

current sources that charge or discharge the external ﬁlter

network connected to the FREQ/PLLFLTR pin. Note that

the LTC3852 can only be synchronized to an external clock

whose frequency is within range of the LTC3852’s internal

VCO.This is guaranteed to be between 250kHz and 750kHz.

A simpliﬁed block diagram is shown in Figure 9.

DIGITAL

PHASE/

FREQUENCY

DETECTOR

VCO

2.7V

RLP

CLP

3852 F09

FREQ/PLLFLTR

EXTERNAL

OSCILLATOR

MODE/

PLLIN

If the external clock frequency is greater than the internal

oscillator’s frequency, fOSC, then current is sunk con-

tinuously from the phase detector output, pulling down

the FREQ/PLLFLTR pin. When the external clock frequency

is less than fOSC, current is sourced continuously, pulling

up the FREQ/PLLFLTR pin. If the external and internal

frequencies are the same but exhibit a phase difference, the

currentsourcesturnonforanamountoftimecorresponding

to the phase difference. The voltage on the FREQ/PLLFLTR

pin is adjusted until the phase and frequency of the internal

and external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and the

ﬁlter capacitor CLP holds the voltage.

Figure 9. Phase-Locked Loop Block Diagram

The loop ﬁlter components, CLP and RLP, smooth out

the current pulses from the phase detector and provide

a stable input to the voltage-controlled oscillator. The

ﬁlter components CLP and RLP determine how fast the

loop acquires lock. Typically RLP is 1k to 10k and CLP is

2200pF to 0.01μF.

When the external oscillator is active before the LTC3852

is enabled, the internal oscillator frequency will track the

external oscillator frequency as described in the preceding

paragraphs. In situations where the LTC3852 is enabled

before the external oscillator is active, a low free-running

oscillator frequency of approximately 50kHz will result. It is

possible to increase the free-running, pre-synchronization

frequency by adding a second resistor in parallel with

RLP and CLP. The second resistor will also cause a phase

difference between the internal and external oscillator

signals. The magnitude of the phase difference is inversely

proportional to the value of the second resistor.

The external clock (on MODE/PLLIN pin) input high

threshold is nominally 1.6V, while the input low threshold

is nominally 1.2V.

Maximum Available Charge Pump Current

For the charge pump, the maximum available output

current and voltage can be calculated from the effective

open-loop output resistance, ROL, and the effective input

voltage, 2VIN1(MIN).

–

ROL

IOUT

VPUMP

2VIN1

3852 F10

–

From Figure 10, the available current is given by:

PUMP =

IN1 –VPUMP

The actual current (into VIN2 and INTVCC) should not

exceed 50mA.

Figure 10. Equivalent Open-Loop Circuit

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