LTM4615 datasheet(20/32 Pages) LINER

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LTM4642

4642fb

For more information www.linear.com/LTM4642

applicaTions inForMaTion

4. θJB, the thermal resistance from junction to the

printed circuit board, is the junction-to-board thermal

resistance where almost all of the heat flows through

the bottom of the µModule and into the board, and

is really the sum of the θJCbottom and the thermal re-

sistance of the bottom of the part through the solder

joints and through a portion of the board. The board

temperature is measured a specified distance from

the package, using a two sided, two layer board. This

board is described in JESD51-9.

A graphical representation of the aforementioned ther-

mal resistances is given in Figure 6; blue resistances are

contained within the µModule regulator, whereas green

resistances are external to the µModule package.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD51-12 or provided in the

Pin Configuration section replicates or conveys normal

operating conditions of a µModule regulator. For example,

in normal board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through bot-

tom of the µModule package—as the standard defines

for θJCtop and θJCbottom, respectively. In practice, power

loss is thermally dissipated in both directions away from

the package—granted, in the absence of a heat sink and

airflow, a majority of the heat flow is into the board.

Within the LTM4642, be aware there are multiple power

devices and components dissipating power, with a con-

sequence that the thermal resistances relative to different

junctions of components or die are not exactly linear with

respect to total package power loss. To reconcile this

complication without sacrificing modeling simplicity—

but also, not ignoring practical realities—an approach

has been taken using FEA software modeling along with

laboratory testing in a controlled-environment chamber

to reasonably define and correlate the thermal resistance

valuessuppliedinthisdatasheet:(1)Initially,FEAsoftware

is used to accurately build the mechanical geometry of

the LTM4642 and the specified PCB with all of the cor-

rect material coefficients along with accurate power loss

source definitions; (2) this model simulates a software-

defined JEDEC environment consistent with JESD51-12

to predict power loss heat flow and temperature readings

at different interfaces that enable the calculation of the

JEDEC-defined thermal resistance values; (3) the model

and FEA software is used to evaluate the LTM4642 with

heat sink and airflow; (4) having solved for and analyzed

these thermal resistance values and simulated various

operating conditions in the software model, a thorough

laboratory evaluation replicates the simulated conditions

with thermocouples within a controlled-environment

chamber while operating the device at the same power

loss as that which was simulated. An outcome of this

4642 F06

µModule DEVICE

JUNCTION-TO-CASE (TOP)

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

JUNCTION

AMBIENT

CASE (BOTTOM)-TO-BOARD

RESISTANCE

Figure 6. Graphical Representation of JESD51-12 Thermal Coefficients

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