LTM2889 datasheet(20/30 Pages) LINER

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LTM2889

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APPLICATIONS INFORMATION

The LTM2889 CAN transceiver also features thermal

shutdown protection that disables the driver in case of

excessive power dissipation during a fault on the CAN bus

(see Notes 3 and 4). When the transceiver die temperature

exceeds 170°C (typical), the transmitter is forced into the

recessive state. All other functions remain active during

the transceiver thermal shutdown, including the CAN bus

receiver and the module isolated communication and

power converter. Other chips in the LTM2889 also contain

thermal shutdown circuits that will shut down all module

operations at approximately 170°C.

Power-Up/Down Glitch-Free Outputs

The LTM2889 CAN transceiver employs a supply under-

voltage detection circuit to control the activation of the

circuitry on-chip. During power-up, the CANH, CANL,

RXD and SPLIT outputs remain in the high impedance

state until the supply reaches a voltage sufficient to reli-

ably operate the transceiver. At this point, the transceiver

activates if RS is low.

The receiver output goes active after a short delay tENRX

and reflects the state at the CAN bus pins, and the SPLIT

output goes active at approximately the same time. The

transmitter powers up in the high-Z recessive state until

the VCC2 supply reaches the power-good voltage, at which

time the transmitter outputs become active and reflect

the state of the TXD pin. This assures that the transmit-

ter does not disturb the bus by glitching to the dominant

state during power-up.

During power down, the reverse occurs; the supply un-

dervoltage detection circuit senses low supply voltage

and immediately puts the transceiver into shutdown. The

CANH, CANL, RXD, and SPLIT outputs go to the high

impedance state. The voltage on RXD is pulled high by

an internal pull-up resistor.

Common Mode Voltage vs Supply Voltage

When operating from the default 5V VCC2 supply voltage

the LTM2889 CAN transceiver adheres to the ISO 11898-2

CAN bus standard by maintaining drive levels that are

symmetric around VCC2/2 = 2.5V with respect to GND2.

An internal common mode reference of VCC2/2 is buffered

to supply the termination of the receiver input resistors. A

second buffer with a high voltage tolerant output supplies

VCC2/2 to the SPLIT output.

If the output from the internal isolated converter is set to

3.3V using a resistor divider on the ADJ pin (Figure 10),

the 2.5V nominal common mode voltage specified in the

ISO 11898-2 standard is too close to the 3.3V supply

to provide symmetric drive levels while maintaining the

necessary differential output voltage. To maintain driver

symmetry the common mode reference voltage is lowered

during 3.3V operation. The typical output common mode

voltage is 1.95V in the dominant state. The internal com-

mon mode reference is set to VCC2/2 + 0.3V = 1.95V to

match the dominant state output common mode voltage.

This reference is independently buffered to supply the

termination of the receiver input resistors and the SPLIT

voltage output.

As the LTM2889 CAN transceiver operates over a very

wide common mode range, this small shift of –0.55V in

the common mode when operating from 3.3V does not

degrade data transmission or reception. An LTM2889

CAN transceiver operating at 3.3V may share a bus with

other CAN transceivers operating at 5V. However, the

electromagnetic emissions (EME) may be larger if trans-

ceivers powered by different voltages share a bus, due to

the fluctuation in the common mode voltage from 1.95V

(when a CAN transceiver on a 3.3V supply is dominant) to

2.5V(whenaCANtransceiverona5Vsupplyisdominant).

RS Pin and Variable Slew Rate Control

The driver features adjustable slew rate for improved EME

performance. The slew rate is set by the amount of cur-

rent that is sourced by the RS pin when it is pulled below

approximately 1.1V (referenced to GND2). This allows the

slew rate to be set by a single slew control resistor RSL

in series with the RS pin (Figure 1).

The relationship between the series slew control resistor

RSL and the transmitter slew rate can be observed in

Figure 13. RSL ≤ 4k is recommended for high data rate

communication. RSL should be less than 200k to ensure

that the RS pin can be reliably pulled below VIL_RS to

enable the chip.

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