LTM2887

22

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APPLICATIONS INFORMATION

Table 3. Unidirectional SPI Timing Event Description

TIME

CPHA

EVENT DESCRIPTION

0, 1

Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns

0, 1

Propagation delay chip select, logic to isolated side

0

Start of data transmission, data set-up

1

Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge

0

Propagation delay of data, logic side to isolated side

1

Propagation delay of data and clock, logic side to isolated side

0, 1

Logic side data sample time, half clock period delay from data set-up transition

0, 1

Clock propagation delay, clock and data transition

0, 1

Data to clock delay, must be ≤13ns

0, 1

Clock to data delay, must be ≤3ns

0, 1

Data and clock propagation delay

0

Last clock and data transition

1

Last clock transition

0

Clock and data propagation delay

1

Clock propagation delay

1

Data propagation delay

0, 1

Asynchronous chip select transition, end of transmission

0, 1

Chip select transition isolated side

terface. Clock (SCL) is unidirectional, supporting master

mode only, and data (SDA) is bidirectional. The maximum

is detailed in Figure 10. The data rate is limited by the slave

2887 F10

SDA

1

8

9

SDA2

SCL

SCL2

START

SLAVE ACK

STOP

clock propagation delay of 225ns, glitch filter and isolated

data delay of 500ns maximum, and the combined isolated

and logic data fall time of 300ns at maximum bus load-