LTM4625 datasheet(13/26 Pages) LINER

13 / 26 page

LTM4625

Rev C

For more information www.analog.com

APPLICATIONS INFORMATION

The RFB(SL) is the feedback resistor and the RTR(TOP)/

RTR(BOT) is the resistor divider on the TRACK/SS pin of

the slave regulator, as shown in Figure 5.

Following the previous equation, the ratio of the master’s

output slew rate (MR) to the slave’s output slew rate (SR)

is determined by:

RFB(SL)

RFB(SL) +60.4k

RTR(BOT)

RTR(TOP) +RTR(BOT)

Forexample,VOUT(MA)=1.5V,MR=1.5V/1msandVOUT(SL)

= 1.2V, SR = 1.2V/1ms. From the equation, we could solve

that RTR(TOP) = 60.4k and RTR(BOT) = 40.2k are a good

combination for the ratiometric tracking.

The TRACK/SS pin will have the 2µA current source on

when a resistive divider is used to implement tracking

on the slave regulator. This will impose an offset on the

TRACK/SSpininput.Smallervalueresistorswiththesame

ratios as the resistor values calculated from the above

equation can be used. For example, where the 60.4k is

used then a 6.04k can be used to reduce the TRACK/SS

pin offset to a negligible value.

Coincident output tracking can be recognized as a special

ratiometric output tracking in which the master’s output

slew rate (MR) is the same as the slave’s output slew rate

(SR), waveform as shown in Figure 6.

From the equation, we could easily find that, in coincident

tracking,theslaveregulator’sTRACK/SSpinresistordivider

is always the same as its feedback divider:

RFB(SL)

RFB(SL) +60.4k

RTR(BOT)

RTR(TOP) +RTR(BOT)

For example, RTR(TOP) = 60.4k and RTR(BOT) = 60.4k is a

good combination for coincident tracking for a VOUT(MA)

= 1.5V and VOUT(SL) = 1.2V application.

Figure 6. Output Coincident Tracking Waveform

Power Good

The PGOOD pin is an open-drain pin that can be used to

monitor valid output voltage regulation. This pin is pulled

low when the output voltage exceeds a ±10% window

around the regulation point. To prevent unwanted PGOOD

glitches during transients or dynamic VOUT changes, the

LTM4625’s PGOOD falling edge includes a blanking delay

of approximately 52 switching cycles.

Stability Compensation

TheLTM4625’sinternalcompensationloopisdesignedand

optimized for use with low ESR ceramic output capacitors.

Table 7 is provided for most application requirements. In

case a bulk output capacitor is required for output ripple

or dynamic transient spike reduction, an additional 10pF

to 15pF feedforward capacitor (CFF) is needed between

the VOUT and FB pins. The LTpowerCAD design tool is

available for control loop optimization.

RUN Enable

Pulling the RUN pin to ground forces the LTM4625 into

its shutdown state, turning off both power MOSFETs and

most of its internal control circuitry. Bringing the RUN pin

above 0.7V turns on the internal reference only, while still

keeping the power MOSFETs off. Increasing the RUN pin

voltage above 1.2V will turn on the entire chip.

TIME

MASTER OUTPUT

SLAVE OUTPUT

4625 F06

LTM4625 датащи(PDF) 13 Page - Linear Technology

LTM4625 датащи(HTML) 13 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

датащи скачать

ссылки URL