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COP680C датащи(PDF) 8 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали COP680C
подробное описание детали  Microcontrollers
PDF  30 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

COP680C датащи(HTML) 8 Page - National Semiconductor (TI)

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COP680CCOP681CCOP682C
Absolute Maximum Ratings
If MilitaryAerospace specified devices are required
please contact the National Semiconductor Sales
OfficeDistributors for availability and specifications
Supply Voltage (VCC)6V
Voltage at Any Pin
b
03V to VCC a 03V
Total Current into VCC Pin (Source)
40 mA
Total Current Out of GND Pin (Sink)
48 mA
Storage Temperature Range
b
65 Cto a140 C
Note
Absolute maximum ratings indicate limits beyond
which damage to the device may occur DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings
DC Electrical Characteristics COP68xC b55 C s TA s a125 C unless otherwise specified
Parameter
Condition
Min
Typ
Max
Units
Operating Voltage
45
55
V
Power Supply Ripple (Note 1)
Peak to Peak
01 VCC
V
Supply Current (Note 2)
CKI e 10 MHz
VCC e 55V tc e 1 ms
80
mA
CKI e 4 MHz
VCC e 55V tc e 25 ms
44
mA
HALT Current (Note 3)
VCC e 55V CKI e 0 MHz
k
10
30
m
A
Input Levels
RESET CKI
Logic High
09 VCC
V
Logic Low
01 VCC
V
All Other Inputs
Logic High
07 VCC
V
Logic Low
02 VCC
V
Hi-Z Input Leakage
VCC e 55V
b
5
a
5
m
A
Input Pullup Current
VCC e 55V VIN e 0V
b
35
b
300
m
A
G Port Input Hysteresis
035 VCC
V
Output Current Levels
D Outputs
Source
VCC e 45V VOH e 38V
b
035
mA
Sink
VCC e 45V VOL e 10V
9
mA
All Others
Source (Weak Pull-Up)
VCC e 45V VOH e 32V
b
9
b
120
m
A
Source (Push-Pull Mode)
VCC e 45V VOH e 32V
b
035
mA
Sink (Push-Pull Mode)
VCC e 45V VOL e 04V
14
mA
TRI-STATE Leakage
VCC e 55V
b
50
a
50
m
A
Allowable SinkSource Current per Pin
D Outputs (Sink)
12
mA
All Others
25
mA
Maximum Input Current (Room Temp)
without Latchup (Note 4)
Room Temp
g
100
mA
RAM Retention Voltage Vr (Note 5)
500 ns Rise and Fall Time (Min)
25
V
Input Capacitance
7pF
Load Capacitance on D2
1000
pF
Note 1
Rate of voltage change must be less than 05Vms
Note 2
Supply current is measured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open
Note 3
The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations Test conditions All inputs tied to VCC L and G ports TRI-STATE
and tied to ground all outputs low and tied to ground
Note 4
Pins G6 and RESET are designed with a high voltage input network for factory testing These pins allow input voltages greater than VCC and the pins will
have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC) The effective
resistance to VCC is 750X (typical) These two pins will not latch up The voltage at the pins must be limited to less than 14V
Note 5
To maintain RAM integrity the voltage must not be dropped or raised instantaneously
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