TABLE 1. Control Register Bits

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DONTC

DONTC

ADD2

ADD1

ADD0

DONTC

DONTC

DONTC

Control Register Bit Descriptions

Bit #:

Symbol:

Description

7, 6, 2, 1, 0

DONTC

Don’t care. The value of this bit does not affect the device.

5

ADD2

These three bits determine which input channel will be sampled and

converted on the next falling edge of CS. The mapping between codes and

channels is shown in Table 2.

4

ADD1

3

ADD0

TABLE 2. Input Channel Selection

ADD2

ADD1

ADD0

Input Channel

0

0

0

AIN1 (Default)

0

0

1

AIN2

0

1

0

AIN3

0

1

1

AIN4

1

0

0

AIN5

1

0

1

AIN6

1

1

0

AIN7

1

1

1

GND

2.0 ADC78H89 OPERATION

The ADC78H89 is a successive-approximation analog-to-

digital converter designed around a charge-redistribution

digital-to-analog converter. Simplified schematics of the

ADC78H89 in both track and hold modes are shown in

Figure 2 and Figure 3, respectively. In Figure 2, the

ADC78H89 is in track mode: switch SW1 connects the sam-

pling capacitor to one of seven analog input channels

through the multiplexer, and SW2 balances the comparator

inputs. The ADC78H89 is in this state for the first three SCLK

cycles after CS is brought low.

The user does not need to worry about any kind of power-up

delays or dummy conversions with the ADC78H89. The part

is able to acquire input to full resolution in the first conversion

immediately following power-up. The first conversion after

power up will be that of the first channel.

Figure 3 shows the ADC78H89 in hold mode: switch SW1

connects the sampling capacitor to ground, maintaining the

sampled voltage, and switch SW2 unbalances the compara-

tor. The control logic then instructs the charge-redistribution

DAC to add or subtract fixed amounts of charge from the

sampling capacitor until the comparator is balanced. When

the comparator is balanced, the digital word supplied to the

DAC is the digital representation of the analog input voltage.

The ADC78H89 is in this state for the last thirteen SCLK

cycles after CS is brought low.

20061609

FIGURE 2. ADC78H89 in Track Mode

20061610

FIGURE 3. ADC78H89 in Hold Mode

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