74HC08 datasheet(2/20 Pages) PHILIPS

2 / 20 page

2003 Jul 25

Philips Semiconductors

Product speciﬁcation

Quad 2-input AND gate

74HC08; 74HCT08

FEATURES

• Complies with JEDEC standard no. 8-1A

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

• Specified from −40 to +85 °C and −40 to +125 °C.

DESCRIPTION

The 74HC/HCT08 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A. The 74HC/HCT08 provide the 2-input

AND function.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns.

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in Volts;

N = total load switching outputs;

Σ(CL × VCC2 × fo) = sum of the outputs.

2. For 74HC08: the condition is VI = GND to VCC.

For 74HCT08: the condition is VI = GND to VCC − 1.5 V.

FUNCTION TABLE

Note

1. H = HIGH voltage level;

L = LOW voltage level.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

74HC08

74HCT08

tPHL/tPLH

propagation delay nA, nB to nY

CL = 15 pF; VCC = 5 V

input capacitance

3.5

CPD

power dissipation capacitance per gate

notes 1 and 2

INPUT

OUTPUT

LLL

LHL

HHH

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