3

dc2150af

DEMO MANUAL DC2150A

Unless otherwise specified, the description of circuit

operation that follows applies to the default assembly

option DC2150A-C.

100V/500ms Surge

In MIL-STD-1275D, the worst-case MOSFET power dis-

sipation condition occurs during the 100V input surge.

The circuit shown in the schematic diagram regulates the

output voltage to 44V. As a result, the circuit must drop

56V from the 100V input to the 44V output. In this MIL-

STD-1275D solution, to increase power available at the

output, two series MOSFETs are used. The first MOSFET’s

(Q3’s) source is regulated to 66V by the LTC4366, while

the second MOSFET’s (Q4’s) source is regulated to 44V

by the LT4363. This reduces the power that must be dis-

sipated in either single MOSFET.

Figures 1 and 2 show the results measured during surge

testing. The oscilloscope waveform in Figure 1 shows this

circuit operating through the full 100V/500ms MIL-STD-

1275D surge requirement. Figure 2 shows this circuit

operating through the less stringent 100V/50ms pulses

described in MIL-STD-1275D’s recommended tests.

±250V Spike and Reverse Input Protection

The 250V spike condition is handled by MOSFET Q3. It

is rated to withstand over 300V from drain to source,

blocking the 250V spike condition seen at the input. MIL-

STD-1275D specifies that the input energy is limited to

15mJ which is easily handled by this MOSFET. Figure 3

shows the results of the 250V spike measured during

MIL-STD-1275D testing.

Similarly, the –250V spike test result is shown in Figure 4.

In this condition, diode D4 is reverse biased during the

–250V spike, blocking the spike from Q4 and the output.

CIRCUIT OPERATION

Figure 1. MIL-STD-1275D 100V/500ms Surge Test

Figure 2. MIL-STD-1275D 100V/50ms Surge

Repeated Five Times

100ms/DIV

20V/DIV

20V/DIV

2A/DIV

100V

43V

4.3A

28V

27V

2.7A

500ms/DIV

20V/DIV

20V/DIV

2A/DIV

28V

27V

27V

27V

2.7A

100V

43V

4.3A

Figure 3. Positive Input Spike

1µs/DIV

50V/DIV

50V/DIV

5A/DIV

250V SPIKE

28V

27V

2.7A

Figure 4. Negative Input Spike

1µs/DIV

50V/DIV

50V/DIV

5A/DIV

−250V SPIKE

2.7A

28V

27V