MPQ4485

– STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS

MPQ4485 Rev.1.0

www.MonolithicPower.com

13

9/18/2017

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© 2017 MPS. All Rights Reserved.

OPERATION

BUCK CONVERTER SECTION

The

MPQ4485

integrates

a

monolithic,

synchronous, rectified, step-down, switch-mode

converter with internal power MOSFETs and

two USB current-limit switches with charging

port auto-detection. The MPQ4485 offers a

compact

solution

that

achieves

6A

of

continuous output current with excellent load

and line regulation over a wide input-supply

range.

The MPQ4485 operates in a fixed-frequency,

peak-current-mode

control

to

regulate

the

output voltage. The internal clock initiates the

pulse-width modulation (PWM) cycle, which

turns

on

the

integrated

high-side

power

MOSFET (HS-FET). The HS-FET remains on

until its current reaches the value set by the

is off, it remains off until the next clock cycle

begins. If the duty cycle reaches 95% (450kHz

switching frequency) in one PWM period, the

current in the power MOSFET cannot reach the

COMP-set

current

value,

and

the

power

MOSFET turns off.

Error Amplifier (EA)

The error amplifier (EA) compares the internal

feedback voltage against the internal reference

power MOSFET current. The optimized, internal

compensation network minimizes the external

component count and simplifies the control loop

design.

Internal VCC Regulator

The 4.6V internal regulator powers most of the

exceeds 4.6V, the output of the regulator is in

1µF ceramic decoupling capacitor.

After the buck output starts up, the internal VCC

LDO output is biased by the buck output

through a Schottky diode.

Enable Control (EN)

The MPQ4485 has an enable control (EN) pin.

An internal

8μA pull-up current allows EN to be

floated for automatic start-up. Pull EN high or

float EN to enable the IC. Pull EN low to disable

the IC.

EN is clamped internally using a 7.6V series

Zener diode and a 10V breakdown voltage of

the ESD cell (see Figure 2).

enhance the EN pull-up current ability. This

requires limiting the EN voltage below 10V or

limiting the EN input current below

500μA if the

EN pull-up voltage is larger than 10V.

EN

Logic

EN

GND

100k

Ω

7.6V

ESD

10V

8µA

Figure 2: Zener Diode between EN and GND

Under-Voltage Lockout (UVLO)

Under-voltage lockout (UVLO) protects the chip

from operating at an insufficient supply voltage.

The UVLO comparator monitors the input

voltage. The UVLO rising threshold is 5V, and

its falling threshold is 4.3V.

Internal Soft Start (SS)

Soft start (SS) prevents the converter output

voltage

from

overshooting

during

start-up.

When the chip starts up, the internal circuitry

generates an SS voltage that ramps up from 0V

to 5V. When SS is lower than REF, the error

amplifier uses SS as the reference. When SS is

higher than REF, the error amplifier uses REF

as the reference. The SS time is set to 2ms

internally.

If the output of the MPQ4485 is pre-biased to a

certain voltage during start-up, the IC disables

the switching of both the high-side and low-side

switches until the voltage on the internal SS

capacitor

exceeds

the

internal

feedback

voltage.