MP103 Rev. 1.01

www.MonolithicPower.com

11

1/23/2014

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OPERATION

MP103 employs a smart inductor-less regulator

design to supply a regulated DC voltage from

an AC input. A unique (patent pending) charge

algorithm transfers charge from the AC line

when the line voltage is below 32V to the VB

capacitor (C1 in the typical application diagram).

The VB capacitor is used as the charge

reservoir for an internal LDO to regulate VOUT.

There are two distinct modes of normal

operation; startup and steady state.

Startup

At start up, all pins are at zero volts, and the AC

line supplies power to VIN through the rectifier.

An internal 19mA current source is enabled

between VIN and DR. This current drives the

base of an external bipolar transistor which

charges the VB capacitor. This internal current

source is only enabled when VIN is within its

charging window, typically below 32V.

This

charging technique minimizes power loss

during start up. During this start up condition,

VB<15.25V, the output regulator is disabled.

As long as VB < 15.25V, DR provides 19mA

during its charging window which limits the

output current if VB is shorted.

When

VB>15.25V, the output regulator is enabled,

and MP103 enters its steady state mode.

IDR

VB

IDR=200mA

Figure 2: Base Current vs. VB Voltage

Steady state

In steady state mode, DR current is increased

to 200mA. Figure 2 depicts the relationship of

the DR/base current to VB voltage.

It is

enabled during its charging window of VIN<

32V.

This technique adaptively replenishes

the VB capacitor charge which supplies power

to the LDO. This enables good efficiency.

An

internal comparator will limit the VB voltage.

These are the VB peak thresholds listed in the

electrical table. This further improves efficiency

by optimally limiting the drop out voltage

depending on VOUT. If VB falls below 7.6V,

the regulator will be disabled, turning off the

power supply.

The EMI performance is

enhanced by turning on and off the current

source at a controlled rate.

The following

sections describe in much more detail the

steady state operation.

Figure 3 depicts the steady state waveforms for

better understanding.

0

v1

v2

v3

VIN

IDR

IIN

t1 t2

t4 t5

t

t

t

0

0

v4

t3

t6

VB

Figure 3: Steady State Waveform

[t1, t2]: At the time of t1, the voltage of VB and

VIN is equal, then VIN is rising higher than VB,

so there will be some charge current flowing

into VB capacitor; At the time of t2, VIN reaches

the slow turn-off threshold, the input current

increased to its maximum value;

[t2, t3]: To benefit the EMI performance, MP103

will turn on and turn off the external BJT slowly

with certain rate. At the time of t2, the driver

reduces the driver current slowly to turn off the

external BJT, at the time of t3, the external BJT

is totally turned off;

[t3, t4]: During this period, the VIN is higher

than the slow turn-off threshold, the driver is

turned off and no current flowing into VB

capacitor, the VB capacitor provides the power

to LDO for output load, at the time of t4, the

voltage

of

VB

drops

from

v2

to

v3;